tag: automatic test equipment

Power-Aware Test Vector Porting For Production ATE
By Hari Mani - 12 Nov, 2024 - Comments: 0

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and frequency scaling (DVFS) can adjust to changing conditions and incrementally adjust power and performance on the fly. Power management starts from the lowest hardware level of transistor structures ... » read more

Advanced Packaging Drives Test And Metrology Innovations
By Gregory Haley - 12 Nov, 2024 - Comments: 0

Advanced packaging has become a focal point for innovation as the semiconductor industry continues to push for increased transistor density and better performance. But the pace of change is accelerating, making it harder for the entire ecosystem to keep up with those changes. In the past, major developments were roughly on an 18-month to 2-year cadence. Today, this is happening every few mon... » read more

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

Supporting Multiple Time Domains In SoC Production Test
By Hari Mani - 14 May, 2024 - Comments: 0

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for defective wafers and assembled chips is always challenging. Production test engineers constantly struggle to minimize expensive test pattern memory, test each wafer or chip as quickly as possible, and... » read more

Battery Management Testing: Alleviating EV Buyer Anxiety
By Thomas Koehler - 14 May, 2024 - Comments: 0

As the electric vehicle (EV) market surges towards 2040, fueled by strong consumer enthusiasm, the need to address key concerns about EV range, reliability, and battery life has become critical. Anxiety over potential range limitations, amplified by fears of scarce charging options, alongside safety worries due to media-reported battery incidents, have slowed adoption rates. Here, the semicondu... » read more

Design Considerations For Ultra-High Current Power Delivery Networks
By Quaid Joher Furniturewala - 11 Jul, 2023 - Comments: 0

This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ. A power-delivery network (PDN), also called a power-distribution network, is a localized network that delivers power from voltage-regulator modules (VRMs) throughout a load board to the package’s chip pads or wafer’s die pads. The PDN includes the VRM itself, all bulk and localized capacitance, board vi... » read more

Device Validation: The Ultimate Test Frontier
By Dave Armstrong - 11 Apr, 2023 - Comments: 0

This article is a condensed version of an article that appeared in the November/December 2022 issue of Chip Scale Review. Adapted with permission. Read the original article at https://chipscalereview.com/wp-content/uploads/flipbook/30/book.html, p. 26. In the early days of space exploration, spacecraft were manned by small teams of astronauts, most of whom were experienced test pilots who ... » read more

Emerging Technologies Are Driving System Level Test Adoption
By Natalian Z. Der - 10 Jan, 2023 - Comments: 0

With the size of semiconductor transistors decreasing and chip complexity increasing exponentially, semiconductor test has become essential to ensuring that only high-quality products go to market. With the introduction of more rigorous acceptable quality level (AQL) certifications, test methods must constantly evolve to meet these standards, and system level test (SLT) and traditional test... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures
By Zhenhua Chen - 06 Dec, 2022 - Comments: 0

This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

Site-To-Site Variation In Parallel Test
By Ed Seng - 16 Mar, 2022 - Comments: 0

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level te... » read more

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