Blog Review: May 5

By Jesse Allen - 05 May, 2021 - Comments: 0

Arm's William Wang considers how to increase the performance and programmability of persistent applications through using battery to protect the on-chip volatile cache hierarchy. Cadence's Paul McLellan finds that ransomware is getting more sophisticated, and more difficult to eradicate and defend against, with potentially life-threatening consequences. Synopsys' Jonathan Knudsen digs int... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 16 Apr, 2021 - Comments: 0

Chipmakers TSMC has posted strong results and raised its capital spending budget to $30 billion, up from its prior guidance of $25 billion to $28 billion in 2021. “Its outlook indicates broad-based semiconductor demand continues to strengthen amid supply chain tightness,” said Weston Twigg, an analyst at KeyBanc, in a research note. “TSMC posted another quarter of strong demand for leadi... » read more

Making Chip Packaging More Reliable

By Mark LaPedus - 15 Apr, 2021 - Comments: 0

Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 02 Apr, 2021 - Comments: 0

Government policy President Biden has rolled out a proposal to boost the infrastructure in the U.S. As part of the plan, the president is calling on Congress to invest $50 billion in U.S. semiconductor manufacturing and research. The proposal must pass Congress, which isn’t going to be easy. “The President’s plan would invest ambitiously in U.S. semiconductor workers, manufacturing, and ... » read more

What Goes Wrong In Advanced Packages

By Ed Sperling - 24 Mar, 2021 - Comments: 1

Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

EUV Pellicles Finally Ready

By Mark LaPedus - 22 Mar, 2021 - Comments: 0

After a period of delays, EUV pellicles are emerging and becoming a requirement in high-volume production of critical chips. At the same time, the pellicle landscape for extreme ultraviolet (EUV) lithography is changing. ASML, the sole supplier of EUV pellicles, is transferring the assembly and distribution of these products to Mitsui. Others are also developing pellicles for EUV, a next-gen... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 19 Mar, 2021 - Comments: 0

Security Infineon announced it has a Trusted Platform Module (TPM 2.0), called OPTIGA TPM 2.0, used to secure remote software updates, disc encryption, and user authentication on Linux-based systems. OPTIGA is an open software stack for securing comprehensive TSS* host software implementing the latest FAPI standard. Infineon developed the open-source software with Intel Corporation and Fraunho... » read more

Defect Mitigation And Characterization In Silicon Hardmask Materials

By Brewer Science - 17 Mar, 2021 - Comments: 0

From SPIE Digital Library: In this study, metal contaminants, liquid particle count and on-wafer defects of Si- HMs and filtration removal rates are monitored to determine the effect of filter type, pore size, media morphology, and cleanliness on filtration performance. 5-nm PTFE NTD2 filter having proprietary surface treatment used in this study shows lowest defect count. Authors: Vineet... » read more

Hunting For Open Defects In Advanced Packages

By Anne Meixner - 17 Mar, 2021 - Comments: 5

Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 05 Mar, 2021 - Comments: 0

Government policy The National Security Commission on Artificial Intelligence (NSCAI) this week submitted its final report to Congress and the President. The goal is to develop a national strategy to maintain America’s AI advantages related to national security. As part of the long and complex report, the NSCAI came to a sobering conclusion: “The U.S. government is not prepared to defend t... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Brewer Science

Blog Review: May 5

Week In Review: Manufacturing, Test

Making Chip Packaging More Reliable

Week In Review: Manufacturing, Test

What Goes Wrong In Advanced Packages

EUV Pellicles Finally Ready

Week In Review: Auto, Security, Pervasive Computing

Defect Mitigation And Characterization In Silicon Hardmask Materials

Hunting For Open Defects In Advanced Packages

Week In Review: Manufacturing, Test