How polar and dispersive components of surface energy can be used to achieve the best lithography performance.
Photoresist and underlayer combine to serve a central role in EUVL for patterning. Layers will be very thin in future, because high numerical aperture (NA) and tight pitches will require very thin layers in the lithography stack. This thinness will make chemical interactions at the photoresist-underlayer interface more common. Adhesion between these layers will be critical to overcome pattern collapse at high aspect ratios whereas at the same time the impact of interfacial effects, such as intermixing, on the lithography performance must be minimized. A fine balance must be found between several chemical interactions, which is a complex exercise with many unknown parameters. In this paper we present how the polar and dispersive components of the surface energy can be used to optimize EUV underlayers in order to achieve the best lithography performance.
Authors:
Click here to read full abstract and access the article page on SPIE’s website.
Steps are being taken to minimize problems, but they will take years to implement.
But that doesn’t mean it’s going to be mainstream anytime soon.
Companies are speeding ahead to identify the most production-worthy processes for 3D chip stacking.
New capacity planned for 2024, but production will depend on equipment availability.
L5 vehicles need at least 10 more years of development.
Increased transistor density and utilization are creating memory performance issues.
Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.
The industry reached an inflection point where analog is getting a fresh look, but digital will not cede ground readily.
100% inspection, more data, and traceability will reduce assembly defects plaguing automotive customer returns.
Engineers are finding ways to effectively thermally dissipate heat from complex modules.
Different interconnect standards and packaging options being readied for mass chiplet adoption.
Steps are being taken to minimize problems, but they will take years to implement.
AMD CTO Mark Papermaster talks about why heterogeneous architectures will be needed to achieve improvements in PPA.
Leave a Reply