tag: Brewer Science

Material Solutions For FOWLP Die Shift And Wafer Warpage
By Shelly Fowler - 20 Jun, 2019 - Comments: 0

By Shelly Fowler Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower-profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-via... » read more

What’s Next In Advanced Packaging
By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 14 Jun, 2019 - Comments: 0

Market research In the second quarter of 2019, TrendForce said that the top-5 foundry rankings remained identical with that of last year. But sixth to tenth place showed some changes. Who is up or down in what is a tough business climate? Global fab equipment spending will rebound in 2020, growing 20% to $58.4 billion after dropping 19% to $48.4 billion in 2019, according to SEMI. However, ... » read more

ECTC Packaging Trends
By Mark LaPedus - 10 Jun, 2019 - Comments: 0

At the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas, a number of packaging houses, R&D organizations and universities presented a slew of papers on the latest IC packaging technologies. The event provided a glimpse of the future of packaging, which is becoming more important in the industry. At one time, IC packaging took a backseat in the semiconductor... » read more

Manufacturing Bits: June 4
By Mark LaPedus - 04 Jun, 2019 - Comments: 0

Chiplet printer A number of companies, R&D organizations and universities separately presented a slew of papers and technologies at the recent IEEE Electronic Components and Technology Conference (ECTC) in Las Vegas. It’s difficult to write about all of the papers at ECTC. But one paper that stood out is a prototype chiplet micro-assembly printer developed by the Palo Alto Research Cente... » read more

Multifunctional Materials Enable Single-Layer Temporary Bonding And Debonding
By Luke Prenger - 23 May, 2019 - Comments: 0

Many new wafer-level packaging (WLP) technologies involve the processing of thin wafers that must be mechanically supported during the manufacturing flow. These technologies include fan-out wafer-level packaging (FOWLP), fan-in wafer-level chip-scale packaging (FI-WLCSP), 3-D FOWLP, 2.5-D integration with interposer technology, and true 3-D IC integration using through-silicon via (TSV) interco... » read more

Controlling IC Manufacturing Processes For Yield
By Ed Sperling - 24 Apr, 2019 - Comments: 0

Equipment and tools vendors are starting to focus on data as a means of improving yield, adding more sensors and analysis capabilities into the manufacturing flow to circumvent problems in real time. How much this will impact the cost of developing complex chips at leading-edge nodes, and in 2.5D and 3D-IC packages, remains to be seen. But the race to both generate data during manufacturing ... » read more

New Plastics Can Speed Flexible Printed Electronics Development
By Tony Flaim - 18 Apr, 2019 - Comments: 0

Substrates play a huge role when designing any type of device, including printed and flexible electronics. From its compatibility with your printing process or with the inks and materials you’re using, to its thermal properties, the choice of substrate can have a significant impact on the effectiveness and manufacturability of your product. However, substrate material capabilities tend to ... » read more

Lithography Options For Next-Gen Devices
By Mark LaPedus - 18 Apr, 2019 - Comments: 2

Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table. For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, w... » read more

Single Vs. Multi-Patterning EUV
By Mark LaPedus - 25 Mar, 2019 - Comments: 5

Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm. Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single pattern... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy