tag: Brewer Science

Realization Of Sub-30-Pitch EUV Lithography Through The Application Of Functional Spin-On Glass
By Brewer Science - 19 Oct, 2022 - Comments: 0

Photoresist metrics such as resolution, roughness, CD uniformity, and overall process window are often aimed to realize the full potential of EUV lithography. From the view of the materials supplier, improvements over the aforementioned metrics can be achieved by optimizing the functional materials used under the resist. The underlayers can significantly enhance the resist performance by provid... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 23 Sep, 2022 - Comments: 0

On Sunday, a 6.8-magnitude earthquake struck the southeast region of Taiwan, causing devastation. TSMC officials reported “no known significant impact for now.” Market research firm TrendForce arrived at a similar conclusion based on its analysis of individual fabs. The Biden administration announced appointment of the leadership team charged with implementing the US CHIPS and Science Ac... » read more

Improving Redistribution Layers for Fan-out Packages And SiPs
By Laura Peters - 15 Sep, 2022 - Comments: 2

Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Big Changes In Architectures, Transistors, Materials
By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

Hybrid Bonding Basics: What Is Hybrid Bonding?
By Jessica Albright - 18 Aug, 2022 - Comments: 2

Hybrid bonding is the key to paving an innovative future in advanced packaging. Hybrid bonding provides a solution that enables higher bandwidth and increased power and signal integrity. As the industry is looking to enhance the performance of final devices through scaling system-level interconnections, hybrid bonding provides the most promising solution with the ability to integrate several di... » read more

Fan-Out Packaging Gets Competitive
By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

A Novel Photosensitive Permanent Bonding Material Designed For Polymer/Metal Hybrid Bonding Applications
By Brewer Science - 18 Aug, 2022 - Comments: 0

Wafer-level hybrid bonding techniques, which provide simultaneous bonding between metal-metal and dielectric-dielectric layers, have attracted more attention in recent years for fabricating 3D integrated circuits with high bandwidth and high interconnect density. However, there are some issues for conventional hybrid bonding using silicon oxide as the dielectric, such as the high stress and low... » read more

Blog Review: Aug. 3
By Jesse Allen - 03 Aug, 2022 - Comments: 0

Siemens' Patrick Hope explains the growing importance of choosing the right laminate for PCB designs and how to read a material datasheet to compare important electrical, thermal, and mechanical properties. Synopsys' Yankin Tanurhan argues that as the number of sensors being integrated in automotive systems increases to enable new ADAS and autonomy capabilities, building security and quality... » read more

Scaling, Advanced Packaging, Or Both
By Ed Sperling - 01 Aug, 2022 - Comments: 0

Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

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