Improving Redistribution Layers for Fan-out Packages And SiPs


Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

How To Compare Chips


Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Big Changes In Architectures, Transistors, Materials


Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

Hybrid Bonding Basics: What Is Hybrid Bonding?


Hybrid bonding is the key to paving an innovative future in advanced packaging. Hybrid bonding provides a solution that enables higher bandwidth and increased power and signal integrity. As the industry is looking to enhance the performance of final devices through scaling system-level interconnections, hybrid bonding provides the most promising solution with the ability to integrate several di... » read more

Fan-Out Packaging Gets Competitive


Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

A Novel Photosensitive Permanent Bonding Material Designed For Polymer/Metal Hybrid Bonding Applications


Wafer-level hybrid bonding techniques, which provide simultaneous bonding between metal-metal and dielectric-dielectric layers, have attracted more attention in recent years for fabricating 3D integrated circuits with high bandwidth and high interconnect density. However, there are some issues for conventional hybrid bonding using silicon oxide as the dielectric, such as the high stress and low... » read more

Blog Review: Aug. 3


Siemens' Patrick Hope explains the growing importance of choosing the right laminate for PCB designs and how to read a material datasheet to compare important electrical, thermal, and mechanical properties. Synopsys' Yankin Tanurhan argues that as the number of sensors being integrated in automotive systems increases to enable new ADAS and autonomy capabilities, building security and quality... » read more

Scaling, Advanced Packaging, Or Both


Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

Fab Investments Head Toward Record High


Corporations and governments around the globe are making record-breaking investments in chip manufacturing plants amid a major push to make the semiconductor supply chain more robust and less prone to shortages caused by everything from market variations to geopolitical interruptions. These investments — which range from updating existing fabrication facilities to building entirely new fab... » read more

Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

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