New Drivers For Test

By Brian Bailey - 28 Jul, 2016 - Comments: 0

Mention Design for Test (DFT) and scan chains come to mind, but there is much more to it than that—and the rules of the game are changing. New application areas such as automotive may breathe new life into built-in self-test (BIST) solutions, which could also be used for manufacturing test. So could DFT as we know it be a thing of the past? Or will it continue to have a role to play? Te... » read more

Accelerating Design-For-Test Pattern Simulation

By Mentor, a Siemens Business - 23 Mar, 2016 - Comments: 0

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Are Chips Getting More Reliable?

By Ed Sperling - 28 Jan, 2016 - Comments: 4

Reliability is emerging as a key metric in the semiconductor industry, alongside of power, performance and cost, but it also is becoming harder to measure and increasingly difficult to achieve. Most large semiconductor companies look at reliability in connection with consumer devices that last several years before they are replaced, but a big push into automotive, medical and industrial elec... » read more

Why Test Is Changing

By Ann Mutschler - 22 Dec, 2015 - Comments: 0

Test is undergoing a revolution in terms of how it is perceived, how it is performed and where it is done. For years, test was something of an afterthought. It was a separate operation that was done after the design was finished, or it was a self-contained module that had to be characterized for power, heat and electrical effects, but not much else. As more chips find their way into markets ... » read more

Advanced IC Packaging Biz Heats Up

By Mark LaPedus - 20 Aug, 2015 - Comments: 0

After a number of false starts and lackluster adoption, the advanced IC packaging market is finally heating up. On one front, for example, a new wave of chips based on advanced [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D"] stacked-die is entering the market. And on another front, the momentum is building for new and advanced 2D packages, such as embedded package-on-package (PoP... » read more

Memory Design At 16/14nm

By Brian Bailey - 28 May, 2015 - Comments: 0

As we get older the memory may start to fade, but that is not a viable option if we are talking about embedded memory. Chips contain increasing amounts of memory, and for many designs memory consumes more than half of the total chip area. “At 28nm we saw a few people with greater than 400Mbits of memory on chip,” says Prasad Saggurti, product marketing manager for Embedded Memory IP at [... » read more

Balancing The Cost Of Test

By Brian Bailey - 23 Oct, 2014 - Comments: 0

As semiconductor devices became larger and more complex, the cost of [getkc id="174" kc_name="test"] increased. Testers were large pieces of capital equipment designed to execute functional vectors at-speed and the technology being used had to keep up with increasing demands placed on them. Because of this, the cost of test did not decrease in the way that other high-tech equipment did. Around ... » read more

Five Disruptive Test Technologies

By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

How Much Testing Is Enough?

By Mark LaPedus - 15 May, 2014 - Comments: 1

As chipmakers move towards finer geometries, IC designs are obviously becoming more complex and expensive. Given the enormous risks involved, chipmakers must ensure the quality of the parts before they go out the door. And as part of quality assurance process, that requires a sound test strategy. But for years, IC makers have faced the same dilemma. On one hand, they want a stringent test me... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution

By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?