Slower Metal Bogs Down SoC Performance


Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

Searching For Power Bugs


How much power is your design meant to consume while performing a particular function? For many designs, getting this right may separate success from failure, but knowing that right number is not as easy as it sounds. Significant gaps remain between what power analysis may predict and what silicon consumes. As fast as known gaps are closed, new challenges and demands are being placed on the ... » read more

Confusion Grows Over Packaging And Scaling


The push toward both multi-chip packaging and continued scaling of digital logic is creating confusion about how to classify designs, what design tools work best, and how to best improve productivity and meet design objectives. While the goals of design teams remains the same — better performance, lower power, lower cost — the choices often involve tradeoffs between design budgets and ho... » read more

Week In Review: Auto, Security, Pervasive Computing


Security A new certification program for hardware verification engineers from Edaptive Computing Inc (ECI) and OneSpin Solutions promises to help companies meet IC integrity standards for SoC designs for 5G, IoT, AI, automotive, industrial, defense, and avionics. These designs are often complex, with a variety of elements, such as programmable logic and different cores. The OneSpin Formal Veri... » read more

Sensor Fusion Challenges In Cars


The automotive industry is zeroing in on sensor fusion as the best option for dealing with the complexity and reliability needed for increasingly autonomous vehicles, setting the stage for yet another shift in how data from multiple devices is managed and utilized inside a vehicle. The move toward greater autonomy has proved significantly more complicated than anyone expected at first. There... » read more

3D PCB Design And Analysis: ECAD/MCAD And Where They Converge


The design of a board and its ‘home’ are heavily interdependent. They require careful consideration to ensure everything will be in working order when your product is ultimately brought to market. Many designs have been derailed by conflicts between ECAD and MCAD. Something as simple as an improperly placed / communicated mounting hole can send your project into a tailspin of re-designs. ... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive The State of California has banned the selling of new vehicles with gasoline-powered internal combustion engines (ICE) by 2035. All new passenger cars sold in 15 years in California will be zero emission cars, according to an executive order signed by the state’s governor. Older ICE passenger cars will still be allowed on the roads and can still be sold as used vehicles. The order... » read more

Have Processor Counts Stalled?


Survey data suggests that additional microprocessor cores are not being added into SoCs, but you have to dig into the numbers to find out what is really going on. The reasons are complicated. They include everything from software programming models to market shifts and new use cases. So while the survey numbers appear to be flat, market and technology dynamics could have a big impact in resh... » read more

5G NR Primer For Amplifier And Filter Design


This primer examines some of the challenges engineers face when designing filters and power amplifiers for 5G New Radio (NR) communication systems. See how the Cadence AWR Design Environment platform can be used to simulate amplifier and filter performance under 5G operating conditions. Click here to continue reading.     » read more

Compiling And Optimizing Neural Nets


Edge inference engines often run a slimmed-down real-time engine that interprets a neural-network model, invoking kernels as it goes. But higher performance can be achieved by pre-compiling the model and running it directly, with no interpretation — as long as the use case permits it. At compile time, optimizations are possible that wouldn’t be available if interpreting. By quantizing au... » read more

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