IoT Has Always Been With Us

By Jeff Dorsch - 10 Oct, 2016 - Comments: 0

By most accounts, Kevin Ashton of the Auto-ID Center at the Massachusetts Institute of Technology coined the term “the Internet of Things” in 1999, referring to a system of ubiquitous sensors connecting the Internet with the physical world. We were well into the 21st century before the Internet of Things, as a marketing term or a short description of a certain technology, came to be wide... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 18 Mar, 2016 - Comments: 0

Intel announced that the company’s former CEO and chairman, Andrew Grove, passed away. He was 79. Present at Intel’s 1968 founding with Robert Noyce and Gordon Moore, Grove became Intel’s president in 1979 and CEO in 1987. He served as chairman from 1997 to 2005. “We are deeply saddened by the passing of former Intel Chairman and CEO Andy Grove,” said Intel CEO Brian Krzanich, in a st... » read more

And the Winner is…

By Brian Bailey - 18 Dec, 2014 - Comments: 0

Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

Architecting For Efficiency

By Ann Mutschler - 10 Apr, 2014 - Comments: 0

By definition, to be efficient is to perform or function in the best possible manner with the least waste of time and effort; having and using requisite knowledge, skill, and industry. As this relates to SoC design today, achieving the highest level of efficiency is a challenge with many dimensions. Efficiency comes in multiple ways. “One dimension would be power consumption,” said Oz Le... » read more

The Rise Of Layout-Dependent Effects

By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Designing for today’s advanced semiconductor manufacturing process nodes brings area, speed, power and other benefits but also new performance challenges as a result of the pure physics of running current through tiny wires. Layout-dependent effects (LDE), which emerged at 40nm and are having a larger impact at 28 and 20nm, introduce variability to circuit ... » read more

Good Pattern Flow Ahead For 14, 10nm

By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Good Times For Analog Designers

By Ann Mutschler - 14 Feb, 2013 - Comments: 1

By Ann Steffora Mutschler For a number of technological reasons, analog/mixed-signal design and low-power design are converging, and with that comes both challenges and opportunities. As far as challenges go, process variations at 14nm, 20nm and even 28nm have increased significantly to include DFM impacts such as layout-delay effects. On the digital side, those process changes affect... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer