Good Pattern Flow Ahead For 14, 10nm

Leading edge manufacturing challenges are driving semiconductor foundries to require more restrictive design rules and new approaches with each new process node.


By Ann Steffora Mutschler
Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node.

“They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant of this shape or this line width or whatever that is creating a yield problem or weak patterns,” observed Michael White, director of product marketing for Calibre physical verification at Mentor Graphics. “Starting at 40nm, even more so at 28nm and that much again at 20nm, is much more orientation-specific layout because folks are using more off-axis illumination. You pay a huge penalty for having optimized the aperture in your scanner for things that are oriented north-south. If you’ve got structures that are east-west they’re not going to resolve as well.”

One approach to deal with these issues termed ‘bad pattern flow’ is based on the idea that the designer can almost do anything they want, but certain 2D patterns are walled off as being bad and forbidden.

Coming at the problem from another perspective is the concept of ‘good pattern flow,’ based on the premise that, “in the future, maybe not everything is going to be manufacturable anymore,” explained Ya-Chieh Lai, engineering director at Cadence. “So the designer is going to be much more constrained moving forward, and the space of the design is really that most things are actually not going to print very well anymore. There’s a sense that maybe we need to have a better understanding of which things do manufacture well and come up with a set of patterns to represent that.”

While not in use at 20nm, this good pattern flow is being readied for the 14nm and 10nm nodes when design rule restrictions become even more severe. But to be enabled in the design flow will require the whole ecosystem to come together, he said.

“We’re working hard on having the core capabilities and tools. We need to work closely with the foundries, because they’re ultimately the source of all of these patterns and a lot of this analysis, to provide the right tools and capabilities to do the kinds of analyses they need to do. We also have to work in conjunction with the design side tools to enable this. This is all a work in progress.”

Specifically, Manoj Chacko, product marketing director at Cadence, pointed out that just as with bad pattern usage, the value to the designer of a good pattern flow is at the routing stage. “Find the issues early on and remove them before going through the signoff. The good pattern flow also mostly fits with the routing side and enforces certain patterns and makes the router enforce certain topologies.”

In terms of where the tools are now, work is being done with the foundries to make sure there is understanding about what the patterns are and how they are used. “A key part of what we are working on here is pattern analysis,” said Lai. “There’s been a lot of talk about pattern matching, but pattern analysis is a bigger story about understanding your layout. The foundries need to understand what designers are doing, be able to understand what patterns are in the design, what are the common cases and the outlier cases to make sure their manufacturing processes are tuned to be able to print what the designers are actually doing. A big part of that is analyzing what is actually in the design.”

Pushback is possible
Mentor’s White expects significant pushback to the good pattern flow strategy. “Over the last couple of years as we’ve been moving pattern matching out into the mainstream use for physical verification, we have some folks who love the ease of use of pattern matching and so on, and their foundry was headed down the path of trying to use more pattern matching to describe actual design rules. The frustration was that, ‘If I’m using patterns to describe only a very finite, small set of things that are manufacturable, you’re taking the design freedom away from the designer.’ They’d far prefer to have the foundry characterizing a broader application space of layout and maintain the designer’s freedom rather than solely focusing their attention on a smaller set of patterns that are known manufacturable.”

Lai agreed there’s always tension about being as restrictive as possible. “If it were up to the foundry they’d just want you to print grading—it’s just going to be straight lines because they know they can print that. But the designers want more flexibility to draw what they need to draw. So what we’re trying to do with the good patterns is to say, ‘We’re going to be as restrictive as possible but then we’re going to allow certain things to be used that would otherwise have been restricted by these restrictive design rules.’ That way it really is meant to help the designer where instead of putting on the brakes and saying, ‘No, you can’t do anything except use these very straight repeated structures,’ we are saying there are going to be certain things that are going to be allowed. These are allowed constructs that you as a designer can put in because this is what you need to make your design work, but everything else is going to be very locked in.”

At the end of the day, “the goal is to minimize patterning,” said Subramani Kengari, vice president of design solutions at GlobalFoundries. “But you also have to optimize a solution. That’s the main reason we’re using wide power rails on standard cells.”

Another consideration: As it stands, not all of the metal layers in a design at 20nm, or even the hybrid 20nm back-end of line (BEOL) process are coupled with 14nm finFETs. But as Moore’s Law continues, more layers will have to be at least double patterned, and with 14nm BEOL some parts of the chip will have to be triple or quadruple patterned.

With this just one example of the complexity that will be faced, a good pattern flow seems more reasonable. And given that designs are becoming much more regular at these advanced nodes is one reason a good pattern flow even becomes a possibility.

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