Good Times For Analog Designers

Analog/mixed-signal design and low-power design are converging, bringing new challenges and opportunities.

popularity

By Ann Steffora Mutschler
For a number of technological reasons, analog/mixed-signal design and low-power design are converging, and with that comes both challenges and opportunities.

As far as challenges go, process variations at 14nm, 20nm and even 28nm have increased significantly to include DFM impacts such as layout-delay effects. On the digital side, those process changes affect performance, and on the analog side it means a change of behavior, noted Qi Wang, technical marketing group director at Cadence Design Systems.

To account for this, designers are using more and more digital circuits or logical controls to compensate for the process variations, a technique referred to as digital assisted analog. The idea is very simple, he said: digital control logic is used to compensate for the process variations to make the analog circuit more stable and more scalable.

In addition, design teams are being challenged with issues pertaining to the area of analog circuitry as a percentage of the available die space. “We have a customer that is moving from 40nm to 28nm and then to 20, and they saw that the percentage of their analog component or mixed signal component as a percentage of the silicon real estate increased dramatically because it doesn’t shrink at the same rate as digital circuitry. By moving more and more of the analog functionality, like peripheral functionality (the core cannot change; the sensing, the RF— there’s no way) but for the rest, like a lot of A-to-D, D-to-A logic put into digital actually also reduces power. It reduces power and reduces the cost of the area of the analog/mixed-signal component. In return, you reduce the cost of the overall IC production,” Wang explained.

All of these issues are forcing analog designers to know more about digital and do mixed-signal design, he said, pointing to companies such as Dialog, ADI and Maxim that have made adjustments in their business strategy in recognition of this.

Because of these challenges, over time analog may be a smaller percentage of the overall design in terms of functionality, but it doesn’t mean its value will fall.

“If you just look at real estate wise on the silicon, definitely the trend is that analog will be less and less as a percentage,” he said. “However in terms of both technology and business level, analog will become a key differentiator for products because analog is magic. If you think about ‘the Internet of things’ it is about sensors, it’s about microcontrollers, it’s about RF components. Of these three key building blocks for the Internet of things, two of them are analog. You cannot replace the sensor with digital because that’s the physical world and the physical world is not digital. RF is communications and you could argue that it could be digital but it is still analog in custom designs—you cannot use standard-cell libraries to build it.”

Navraj Nandra, senior director of marketing for DesignWare Analog and MSIP at Synopsys, agreed: “The manufacturing requirements on these smaller technology nodes means that the design rules become quite restrictive and that means that you end up having to make layouts that are maybe the same size as previous node or in some cases bigger—so that’s a purely engineering point of view. When you go to a customer and discuss this it’s not acceptable because se they’ve heard all these presentations at conferences that Moore’s Law is still alive and well, that we can support Moore’s Law down to 7 nm.”

One of the main reasons for moving SoCs to the next process node is to cram more functionality onto a single chip.

“If you are basically saying, ‘If you want to have USB or some kind of analog/mixed-signal functionality it may not meet the area target,’ that becomes unacceptable to the SoC developer,” Nandra said. “Understanding that, we try to find a way to get the area down and so far we’ve been successful but it’s not a simple activity like it is in the digital world where you basically call up a set of libraries can pick your EDA tool and it will build you a circuit that is smaller. You have to go back and redo the architectures.”

Nandra noted that digital techniques are becoming more common in smaller technology nodes for analog blocks. “We’re seeing the amount of digital increasing in analog circuits so the design goal for analog designer, especially if they are trying to meet all the SoC area requirements in the next technology node, is to see how much of the problem they can solve in the digital world.”

There are three benefits to this. First, if it’s in the digital world it will scale. Second, digital circuits aren’t as impacted by process voltage and temperature changes. Third, the essential circuits aren’t impacted by noise as much as analog circuits. So if that problem can be solved in the digital world it can eliminate a lot of other problems, as well.

“Just looking at new architectural techniques, I think 14nm is going to be interesting because the transistor characteristics are different,” Nandra said. “There’s going to be quite a bit of invention in the next few years where analog designers are going to look at the properties of the finFET device because they are different than the planar device and say, ‘Oh, this is interesting. Maybe I can solve this particular design problem by using this finFET transistor in this particular configuration.’”

Analog scaling using digital techniques (Source: Synopsys)

Simulation for all
Smaller process nodes bring changes on many levels. Historically, most designs migrated to lower process nodes because of cost and performance, but recently it has become clear that the move to lower process nodes is due to power, cost and performance concerns.

“Power has been one of the largest driving factors for people to adopt 20nm. To look at today’s 20nm it is offering more than 25% reduction in terms of power from the previous node—that’s one of the biggest reasons why we are seeing customers going to the 20nm node,” said Arvind Shanmugavel, director of applications engineering at Apache Design.
“That being said, we also see higher levels of integration. If you look at today’s processors they are not standalone digital devices. They have multiple shared analog components on the same piece of silicon. If you look at an application processor for example, it’s got a GPS module, it’s got a radio, it’s got high-speed I/O, data converters—everything built into the same piece of silicon shared along with your digital microprocessor. We are seeing a different set of challenges both in terms of power management, in terms of reliability of these ICs, in terms of how to simulate them with the proper context of digital plus analog plus the entire system operating in unison.”

Specifically with regard to analog, some designers have encountered challenges, especially at 20nm. “Our customers are coming to us and saying that they are not able to have much leverage in terms of designing devices that have good length and width control— they can only design devices that have a multiple of a certain width and multiple of a certain length. That’s essentially because of the 20nm requirements,” Shanmugavel said.

Then on the reliability side, for power management ICs in the 20nm node the electromigration rules are 30% more stringent than at the 28nm node. “Designing a processor from the 28nm node going to 20nm was more than a speed bump; you are basically looking at a 30% reduction in the electromigration margins so that is one big aspect that our designers are facing—and it’s a big challenge,” he continued. That doesn’t even include other aspects such as ESD and EMI.

The answer, Shanmugavel believes, is a simulation-driven approach to design rather than the prevailing correct-by-construction approach. “Historically, we have seen most of the design tools do a correct-by-construction approach but with the margins in electromigration and ESD or even margins such as EMI, they have been reducing so dramatically, the designer of these ICs have to simulate these ICs with the proper conditions and then do their design. They cannot assume that they have enough margin and signoff on a particular criteria.”

Even with the challenges, the future looks bright. “It’s a great time to be an analog designer,” said Synopsys’ Nandra. “You’ve got the possibility now to really invent some new circuits because analog design, by its nature, involves very close interaction with the transistor properties as opposed to digital design. The whole point of digital design is to be far away from the transistor property. But with analog design you’re looking at the thousands of different states one transistor can actually be in. There are going to be some very interesting new circuits coming up and it’s going to be a challenge to find lots of creative analog designers because for many years the whole industry has pushed engineering towards big digital design.”