tag: Cadence

What Happened To Portable Stimulus?
By Brian Bailey - 28 Sep, 2023 - Comments: 0

In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

Use Tcl To Save Signals More Efficiently In AMS Simulations
By Qingyu Lin - 28 Sep, 2023 - Comments: 0

Saving signal waveforms during a simulation is one of the basic ways to check the simulation results. However, with large SoC designs, it’s not always practical to save all signals during simulation, and the simulation performance might also be impacted by the number of signals being saved. Therefore, a crucial part of the simulation setup is to specify the expected and essential signals to s... » read more

Blog Review: September 27
By Jesse Allen - 27 Sep, 2023 - Comments: 0

Siemens' Dirk Hartmann examines how a continual improvement in predictive capability processing and algorithms enables the evolution of simulation performance and highlights two areas that underpin most simulation tools. Synopsys' Ian Land, Jason Niatas, and Marc Serughetti note that digital twins can be used from the chip level through sub-systems and up to the system level to examine perfo... » read more

Data Management Challenges In Heterogeneous Systems
By Ed Sperling - 27 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss issues in smart manufacturing of chips, including data management, chiplets, and standards, with Mujtaba Hamid, general manager for product management for secure cloud environments at Microsoft; Vijaykishan Narayanan, vice president and general manager of India engineering and operations at proteanTecs; KT Moore, vice presiden... » read more

Unleashing The Power Of Generative AI In Chip, System, And Product Design
By Cadence - 27 Sep, 2023 - Comments: 0

The field of chip, system, and product design is a complex landscape, fraught with challenges that designers grapple with daily. The traditional design process, while robust, often falls short in addressing the increasing demands for efficiency, customization, and innovation. This white paper delves into these challenges, exploring the transformative potential of generative artificial int... » read more

Chip Industry Week In Review
By The SE Staff - 22 Sep, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan The U.S. Department of Defense (DOD) announced $238 million in awards toward establishing eight regional innovation hubs under the CHIPS and Science Act. The hubs aim to accelerate hardware prototyping and "lab-to-fab" transition of semiconductor technologies for secure edge/IoT, 5G/6G, AI hardware, quantum technology, electromagnetic warfare, and ... » read more

Blog Review: September 20
By Jesse Allen - 20 Sep, 2023 - Comments: 0

Siemens' Patrick Hope considers the unique attributes of materials used in flex and rigid-flex PCB designs and how they are constructed. Synopsys' Kenneth Larsen and Shekhar Kapoor find that the increased impact of thermal, signal integrity, and other multi-physics effects on multi-die systems calls for looking at the whole system, from technology to dies and package together. Cadence's V... » read more

Chip Industry Week In Review
By The SE Staff - 15 Sep, 2023 - Comments: 0

By Gregory Haley, Jesse Allen, and Liz Allan TSMC told equipment vendors to delay deliveries of the most advanced tools due to uncertain demand, according to Reuters. The news drove down stock prices of all the major equipment providers. On the other hand, TSMC said advanced packaging shortages will constrain AI chip shipments for the next 18 months, according to NikkeiAsia. The United St... » read more

LLM Technology For Chip Design
By Steve Brown - 14 Sep, 2023 - Comments: 0

In the nine short months since OpenAI brought ChatGPT (a Chat Generative Pre-Trained Transformer) and the phenomenal concept of large language models (LLMs) to the global collective consciousness, pioneers from every corner of the economy have raced to understand the benefits—and the pitfalls—of deploying this nascent technology to their particular industry. And as it turns out, semicondu... » read more

Managing P/P Tradeoffs With Voltage Droop Gets Trickier
By Ann Mutschler - 14 Sep, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop/IR drop with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight Technologies; Venkatesh Santhanagopalan, product manager at Movellus; Joe Davis, senior director for Calibre interfaces and mPower EM/IR... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy