Executive Briefing: Lip-Bu Tan


By Ed Sperling LPHP: From a high level, what are your customers doing differently these days? Tan: What system companies are looking for is time-to-market and differentiation. They want to differentiate on specific functions. IT has become very important in this process. And in terms of tools, they are looking for end-to-end solutions. Besides the advanced nodes and IP blocks, they are starti... » read more

Dealing With The Data Glut


By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more

Experts At The Table: FinFET Questions And Issues


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts ... » read more

Diverging Viewpoints


By Ed Sperling The raw materials of semiconductor design include smart, well-trained people and money to fund good ideas from those people, whose backgrounds typically come from engineering, math, physics, computer science, materials science and sometimes even chemistry. While many experts, executives, and industry groups have been sounding the alarm in recent years about everything from la... » read more

The Smartphonification Of Things


By Ann Steffora Mutschler The term, ‘Internet of Things,’ was first coined more than a decade ago by technology visionary Kevin Ashton but has slowly trickled down to the world of chip design and is now mentioned constantly in conversation. The reason is simple: System-level design tools are getting sophisticated enough to handle the intricacies required by devices in an Internet of ... » read more

More Than Data Management


By Ann Steffora Mutschler Managing the people, the data and the technology are just as important as meeting the market window given that without these, the entire project wouldn’t function. Throw huge data set sizes, different cultures and business management issues into the mix and the challenges are many. Fortunately, these are issues that the semiconductor industry has been refining for ... » read more

Continuous, Connected And Concurrent Verification


By Ed Sperling It’s a wonder that any electronic system works as intended, or that it continues to work months or years after it is sold. The reason: SoCs have become so complex that no verification coverage model is sufficient anymore, no methodology covers every aspect of verification, and no single tool or even collection of tools can catch every bug or prevent them from being there in th... » read more

Observation Post


By Pranav Ashar After attending the 2013 Design and Verification Conference (DVCon) in San Jose, Calif., I have compiled notes as both an observer and a panel participant. Here are my observations: Wally Rhines, CEO of Mentor Graphics, gave the keynote presentation: Accelerating EDA Innovation Through SoC Design Methodology Convergence. Logically and effectively he made the case that SoC in... » read more

Staying Neutral


By Kurt Shuler It’s official: The great IP land grab has begun. The process actually has been taking place gradually, but has accelerated with Imagination Technologies’ acquisition of MIPS last year and, most recently, Cadence’s acquisition of Tensilica. For makers of semiconductors, four competing IP behemoths are emerging after years of fragmentation within the semiconductor IP indu... » read more

Market Realities


The speculation about EDA’s future—will it consolidate, will it be incorporated into large IDMs or foundries—has surfaced again. The reason this time is that EDA is in a retrenchment period as the semiconductor industry grapples with increasing complexity, multiple options ranging from multi-patterning to stacked die to more third-party IP, and the rising cost of complex SoCs at the mo... » read more

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