tag: Cadence

Mythbusting: Co-Design
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler It turns out that while there needs to be understanding between hardware and software engineers, the people doing the programming don’t actually want or need to interact. There is not, nor probably ever will be, one single team with hardware and software engineers happily working together on a project. But it’s not a total disconnect. There are a number o... » read more

Surprises Abound As Subsystem IP Gains Prominence
By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

Development Tools Enabling The Internet of Things
By Frank Schirrmeister - 27 Feb, 2013 - Comments: 0

I'm at the Embedded World conference in Nuremberg this week. Yes, between Mobile World Congress in Barcelona and DVCon in San Jose, Calif., I chose Embedded World. Unfettered by unseasonally late snow and bad weather, it turns out this was the right decision. I have not attended this show for a couple of years and am pleased to find that the show has developed quite a bit. There are more than 8... » read more

Accelerating Moore’s Law
By Ed Sperling - 21 Feb, 2013 - Comments: 0

By Ed Sperling Ever since the inception of Moore’s Law, process nodes have moved forward at a rate of once every 18 to 24 months. Companies have been talking about slowing down the rate of progression as things get harder, but at least for the next couple of process nodes something very strange will occur—Moore’s Law will accelerate. The root cause is growing competition for a shrinki... » read more

A Call To Action: How 20nm Will Change IC Design
By Various Writers - 21 Feb, 2013 - Comments: 0

The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a �... » read more

SOI Highlights at Common Platform Tech Forum
By Various Writers - 19 Feb, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a ... » read more

Raising The Stakes For IP
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market. The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occu... » read more

Too Hot To Handle
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler It used to be that a device could be designed to a thermal design power. The worst case power scenario would be imagined, and the device would be designed with that in mind. But those good old days are gone. Especially for consumer devices, how a device is going to behave with respect to time, or how people are going to use it, must be understood as completely a... » read more

New Issues In Signoff
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Signoff has always been a challenge at every stage of an SoC design flow. No matter how good a design looks, or how well a prototype works, there are still problems that can crop up at any stage of the design flow all the way into manufacturing that can leave engineering teams shaking their heads. Even at mainstream process nodes, respins are common. At advanced nodes—part... » read more

Sprint To The Finish Line
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: Has the move to 20nm processes with 14nm finFETs progressed as smoothly as everyone hop... » read more

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