Sprint To The Finish Line

First of two parts: No one knows where the real end of Moore’s Law is yet, but the race is on to get there—and bring key pieces of the ecosystem along with it.

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By Ed Sperling
Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation.

LPHP: Has the move to 20nm processes with 14nm finFETs progressed as smoothly as everyone hoped?
Hsu: We’ve been doing a few “vertical” collaborations with the foundries.

LPHP: That’s vertical as in a virtual IDM model?
Hsu: Yes. They’ve shifted from a horizontal model, which included services and EDA and foundries. Between the segmentation, there needs to be tremendous collaboration. When the foundry sends out a PDK file and it doesn’t work, who do you talk to? Is it the tool vendor? The foundry? IP is another problem. IP, EDA and the foundry are the three elements of this vertical collaboration. You can’t separate them anymore. A few years ago we focused on vertical collaboration in my team. Just for the collaboration we invest a lot of resources every year.

LPHP: That’s just to keep the collaboration working?
Hsu: Yes. This is not about developing tools or features. It’s purely collaboration. We have more than 20 projects with one company. It’s a big effort. In 2012, we also had close to 20 marketing events and technical papers. That work is related to test chips and real silicon.

LPHP: To get to stacked die over the next few years, the relationships in the supply chain have to be much tighter. Is this changing?
Hsu: One of the issues is known good die. If you get everything from one company, that’s not a problem. Otherwise, you will need a very deep collaboration with suppliers. Foundries have a short list of suppliers who will work together to make sure the infrastructure is in place. The cost of the 3D package is still a concern, though.

LPHP: Does the relationship you have with foundry partners carry over into the stacked die world, as well?
Hsu: Absolutely, and it’s because we do real work in this area. We started on 3D-IC in 2007. I was running IC R&D when someone came back and said we need to do this 3D-IC. My question was how many licenses we can sell. But the company was committed. That’s how we started. Finally, six-plus years later, we are getting closer. We’ve already done several 3D-ICs. We’ve actually manufactured them and tested them.

LPHP: How does that look in terms of performance and energy efficiency?
Hsu: From an integration standpoint—mixing RF and analog—it’s very hard to optimize a process to address all of them at the same time. From that perspective, the flexibility and the integration is absolutely there. And we’ve proven the technology can be done. The whole industry is struggling with the infrastructure and the business model right now. If it doesn’t work, who pays for it? But from the standpoint of energy efficiency and performance, there is absolutely a benefit. You can still do some things on the die directly, but if it’s that much cheaper and more reliable, it’s preferable.

LPHP: As we move down to the next nodes, though, with multi-patterning and RC delay in the wires and interconnects, does this get more attractive?
Hsu: It’s amazing how the process engineer has been able to solve those problems incrementally. There is a physical limit somewhere. We don’t know where that is. We started with 20nm three years ago, and one of the first things the foundries worry about is when they have their process ready is whether we can design to it without too much penalty. The rules are so complex, can anyone design with the intended density in mind? We‘ve reached our target, where it is economically attractive.

LPHP: But at some point the cost of shrinking will become economically unattractive, right?
Hsu: Yes, but the tail is always longer than you expect. A large part of this has to do with how good the design tools are. If you can design with efficiency, without margin and the resistivity in different layers and layout-dependent effects, that’s the best. The easiest way to make sure it works is to make sure the chip works is to separate everything far apart because then you don’t have layout-dependent effects. But that defeats the purpose of density. So the question is whether you can reduce the penalty over design efficiency. Because of our tight collaboration, we have reduced out penalty significantly.

LPHP: For which node?
Hsu: 20 nanometer.

LPHP: What happens at 14?
Hsu: 14 adds more complexity. But with finFETs, it’s more a question of how you design with the material. The 3D transistor has a lot of parasitics. If it’s just in the routing of the signal, that’s one thing. But if the parasitics are in the gate and source and drain, it changes the behavior of the transistor. That adds a lot more rules. How can you design in a way so that it voids the majority of those issues? The cell has more restrictions. And how you access the pins has more restrictions. The place and route automation has more restrictions.

LPHP: A big issue for EDA has been how far to extend the R&D budget into future nodes compared with what makes current nodes better. How do you deal with that?
Hsu: We do quite well with where most of our customers are, which is 28, 40, 65nm. There’s still a lot of that. For Cadence, R&D is heavily customer-driven. If someone has a problem in the middle of a tapeout, we jump. With that in mind, we’re constantly being pushed by customers because designs are competing with each other. The whole thing is moving forward around those things.

LPHP: How about FD-SOI?
Hsu: Some people look at FD-SOI as a temporary benefit. Sooner or later they will have to do finFETs, anyway. FinFETs are a different process. Once you commit to something, you have to develop all the different IP. If it’s just for one node, you get all the training and tools with it.

LPHP: How much do the tools and IP have to change with FD-SOI?
Hsu: Not that much because it’s still planar. The SPICE model is different, but the process is still incremental. With finFETs, it’s a jump. For those people who aren’t doing SOI, though, putting up a fab that can do it is a huge investment. If that huge investment is only one or two nodes, it’s hard to justify.

LPHP: For the first time, there are multiple options. There is FD-SOI, finFETs and stacked die. Is that enough to say you have enough headroom to say you don’t have to progress as quickly in the future?
Hsu: We believe that at some point the process nodes will slow down. Whoever has the best technology to address that last node will win in the marketplace.

LPHP: But you still may have a 7nm logic platform in a stacked die, right?
Hsu: Yes, and we believe that all of those technologies may be viable. But they will slow down for the mass market for a given time. So whoever is there first has the opportunity to take the most market share. By the time the others invest it will be too late.