tag: CEA-Leti

Stacking Logic On Logic
By Katherine Derbyshire - 21 Jul, 2016 - Comments: 0

Advanced packaging can be an alphabet soup of possible approaches, from heterogenous integration of multiple die types into a single package, to three-dimensional stacking of multiple dies on top of each other. Three-dimensional chip stacking is most commonly seen in memory devices. Applied to logic, though, there are at least two different ways for integration to proceed. Completely process... » read more

FD-SOI Strains For The Future
By Katherine Derbyshire - 11 Jul, 2016 - Comments: 0

One of the challenges facing supporters of FD-SOI is the need to provide a pathway to improved performance. While FD-SOI wafers offer some significant advantages over bulk silicon wafers, performance enhancements like strain and alternative channel materials are more difficult to implement in the thin SOI environment. On the other hand, once a fab is willing to incorporate layer transfer techni... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 08 Jul, 2016 - Comments: 2

Fab materials/tools The Reference Project, a pan-European research program created to develop radio-frequency silicon-on-insulator (RF-SOI) technology, was recently launched at the Bernin, France-based facilities of Soitec. Soitec is the project leader in the group, which has an eligible budget of 33 million euros. The project will focus on developing technologies for 4G+ communications usi... » read more

Pathfinding Beyond FinFETs
By Paula Doe - 13 Jun, 2016 - Comments: 0

Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

Building A Better Resonator
By Katherine Derbyshire - 19 May, 2016 - Comments: 0

The resonant frequency of a beam depends on the mass and stiffness of the beam. Resonance has always been important in the design of musical instruments and amplification systems, as well as the design of bridges and buildings. With the advent of MEMS fabrication techniques, though, came the ability to create very small beams, in the micron or nanometer size range, with resonant frequencies ... » read more

Manufacturing Bits: March 29
By Mark LaPedus - 29 Mar, 2016 - Comments: 0

Brain-inspired computing Lawrence Livermore National Laboratory (LLNL) has purchased a brain-inspired supercomputing platform for deep learning developed by IBM Research. Based on a neurosynaptic computer chip called IBM TrueNorth, the scalable platform will process the equivalent of 16 million neurons and 4 billion synapses. It will consume the energy equivalent of a tablet computer. ... » read more

Manufacturing Bits: March 15
By Mark LaPedus - 15 Mar, 2016 - Comments: 0

More multi-beam The multi-beam e-beam market is a hot topic. For example, Intel is quietly in the process of acquiring IMS Nanofabrication, a developer of multi-beam e-beam tools for mask writing applications. Meanwhile, at the recent SPIE Advanced Lithography conference, Mapper Lithography disclosed new upgrades for its multi-beam e-beam tool for use in direct-write lithography application... » read more

Manufacturing Bits: March 8
By Mark LaPedus - 08 Mar, 2016 - Comments: 1

5G mmWave consortium Amid a slowdown in the cell phone business, the market is heating up for perhaps the next big thing in wireless—5th generation mobile networks or 5G. Carriers, chipmakers and telecom equipment vendors are all rushing to get a piece of the action in 5G, which is the follow-on to the current wireless standard known as 4G or long-term evolution (LTE). Radio-frequency (RF... » read more

Internet of FD-SOI Things?
By Katherine Derbyshire - 18 Feb, 2016 - Comments: 0

Are fully-depleted silicon-on-insulator (FD-SOI) wafers having a moment? Certainly SOI wafers are not new. Soitec’s SmartCut layer transfer technology was patented in 1994, and wafers with implanted oxide layers were available before that. Still, adoption of SOI wafers has been limited. Though they offer improved device isolation and reduced parasitics, the increased wafer cost has been an ob... » read more

Manufacturing Bits: Feb. 9
By Mark LaPedus - 09 Feb, 2016 - Comments: 1

3D chip consortium The 3D integration consortium of IRT Nanoelec has a new member--EV Group. Based in Grenoble, France, IRT Nanoelec is an R&D center headed by CEA-Leti. Formed in 2012, the 3D integration consortium is one of IRT’s core programs. EV Group joins Leti, Mentor Graphics, SET and STMicroelectronics as members of the 3D consortium. The program is developing a 3D integration ... » read more

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