tag: CEA-Leti

SEMICON West Preview
By SEMI - 19 May, 2014 - Comments: 0

By Paula Doe The fast growing demand for bandwidth is driving telecomm and data center user interest in moving high speed optical connections closer and closer to the chips, as recent advances in packaging technology, from microbumping to bonding to wafer-level redistribution now help make it possible. Chip-to-chip and chip-to-board optical connections increasingly look like a viable soluti... » read more

Billions And Billions Invested
By Mark LaPedus - 17 Apr, 2014 - Comments: 4

Over the years, next-generation [getkc id="80" kc_name="lithography"] (NGL) has suffered various setbacks and delays. But until recently, the industry basically shrugged its shoulders and expressed relatively little anxiety about the NGL delays. After all, optical lithography was doing the job in the fab and NGL would eventually materialize. Today, however, the mood is different. In fact, th... » read more

Directed Self-Assembly Gains Momentum
By Mark LaPedus - 20 Mar, 2014 - Comments: 0

At last year’s SPIE Advanced Lithography symposium, directed self-assembly (DSA) grabbed the spotlight as chipmakers provided the first glimpse of their initial work and results with the technology. The results were stunning, thereby propelling DSA from a curiosity item to a possible patterning solution for next-generation devices. Last year, in fact, GlobalFoundries, IBM, Intel and Sams... » read more

Under The Radar At SPIE
By Mark LaPedus - 20 Mar, 2014 - Comments: 2

At the SPIE Advanced Lithography symposium, the best and brightest minds in the lithography, metrology, resist and design-for-manufacturing (DFM) fields assemble for a week. The annual event is a good way to get a pulse on the current state of lithography. At this year’s SPIE, it was simple to get a reading. Extreme ultraviolet (EUV) lithography remains delayed. The other next-generation l... » read more

Manufacturing Bits: Feb. 25
By Mark LaPedus - 25 Feb, 2014 - Comments: 0

Intel joins DSA consortium Arkema, ASML, Intel and others have formed a new consortium in the emerging directed self-assembly (DSA) arena.The group, dubbed PLACYD, is a European funded consortium. Part of the Seventh Framework European Programme (FP7) and funded by ENIAC JU (European Technology Platform for Nanoelectronics), the project includes Arkema, CEA-Leti, STMicroelectronics, Intel,... » read more

Week In Review: Manufacturing, Design, Test
By Mark LaPedus - 21 Feb, 2014 - Comments: 0

Reports have surfaced that IBM’s semiconductor unit is on the block, and there has been discussion about the reasons and the aftermath. Sources say there are at least two potential buyers for the unit—Samsung and TowerJazz. Apparently, the talks between IBM-Samsung and IBM-TowerJazz have been going on for some time. Multiple sources believe that Samsung is interested in buying IBM’s advan... » read more

Manufacturing Bits: Feb. 11
By Mark LaPedus - 11 Feb, 2014 - Comments: 1

Monolithic 3D SRAM project A group of companies have started a research project to propel the development of monolithic 3D chip technology. The research project, called COMPOSE³, involves the ability to stack transistors vertically. Within three years, the group hopes to unveil a proof of concept for building the world’s first 14nm, 3D-stacked SRAM cell based on III-V materials. Co... » read more

DSA, Multi-beam Make Steady Progress
By Mark LaPedus - 12 Dec, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss current and future lithography challenges with Laurent Pain, lithography lab manager at CEA-Leti. What follows are excerpts of that conversation. SE: CEA-Leti has two major programs in lithography. One is in directed self-assembly (DSA) and the other is in multi-beam e-beam. Let’s start with multi-beam. What is Leti doing in multi-beam and what... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

Tunnel FETs Emerge In Scaling Race
By Mark LaPedus - 14 Nov, 2013 - Comments: 2

Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers. In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate... » read more

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