SEMICON West Preview

Chip-to-chip optical connections get close to market with multiple different technologies.


By Paula Doe
The fast growing demand for bandwidth is driving telecomm and data center user interest in moving high speed optical connections closer and closer to the chips, as recent advances in packaging technology, from microbumping to bonding to wafer-level redistribution now help make it possible.

Chip-to-chip and chip-to-board optical connections increasingly look like a viable solution within the next few years to the input/output roadblock as telecommunication networks and data centers strive to handle the big growth in demand for bandwidth. But there’s still plenty of disagreement on just how to best to make them. We’ve invited some of the leading developers to SEMICON West 2014 to discuss their progress towards integrating optics with electronics, both at the package level and the wafer level.

Among the package-level solutions is one from Compass-EOS, which is currently shipping commercial routers with optical connections between the processor chips in the backplane, made by packaging standard optical die in a module with the controlling ASIC. “We don’t do classical silicon photonics—no wave guides or modulators on silicon,” explains Shuki Benjamin, process engineering manager at the Israeli startup, who will speak at the program. “We put conventional VCSELs and photo diode matrices on the silicon, and then take the information in and out of the silicon as light.” The company’s investors include Comcast and Cisco.

The chip assembly technology, developed in collaboration with the Fraunhofer Institute in Berlin, essentially flip chips the optical die to the ASIC with gold pillar bumps, similar to how III-Vs have long been flip-chipped on silicon for military IR detectors for night vision. “We use conventional equipment, but not conventional processes,” says Benjamin.

Analog circuitry included on the processor handles the conversion between optical and electronic signals coming in and out of the chip. The optics-on-ASIC unit is mounted on an organic interposer with a cutout hole to expose the optical dies, and the whole module is then mounted with conventional SMT technology over the cutout in the printed circuit board. There the array of laser and photo diode light pixels are aligned with a matching array of fiber ends in a custom silicon ferrule in the fiber optic bundle. The optical design is a two-lens relay system, where the light coming out of the VCSEL or fiber is collimated in the first lens and then focused in a second into the fiber or photo-diode respectively. This design allows for a very loose tolerance in assembly. A series of these modules creates a full-mesh direct optical link with multimode fibers between multiple processors in the company’s router.

Initial customers are telecommunications network users, including NTT Communications and a Tier 1 telecom player in the United States and the Australian system integrator COMDATE, with other users in the United States and Japan now testing the equipment. “The main driver is that it allows the system to be smaller and to use less energy,” says Benjamin.

The company currently is doing the wafer-level processing and bumping at a commercial fab, and doing the assembly in house, but looking to move assembly to an OSAT partner to ramp up volume. “Volumes are low to start, since it’s for a router, but as the manufacturing proves itself other applications will arise in big servers that have to move information at high rates,” he suggests. “We believe that in the future more and more dies will have some sort of optical connection to enable high bandwidth data exchange, and we think this technology could help enable it.”

CEA-Leti and partners opt for wafer-level integration
CEA-Leti, on the other hand, molecularly bonds the III-V laser material directly to the silicon for processing at the wafer level, and reports state-of-the-art 10% wall-plug efficiency for this hybrid laser on silicon.

“We think we have a very cost effective process,” says Sylvie Menezo, head of the Integrated Photonics Programs at Leti, who will update on their progress at SEMICON West. They grow the III-V gain layers on an InP substrate, then bond the die face down all at once to a silicon wafer on which modulators and photo detectors are already patterned. Alignment requirements are quite relaxed at ~50µm. Then the InP substrate is removed, and the bonded III-V die are further processed in a regular wafer-level process flow. Putting the expensive compound semiconductor material only where needed saves on cost, as does doing the laser processing at the wafer level, and potentially re-using the removed InP handle substrate. This photonic chip is then integrated with the electronics with a variant of Leti’s 3D packaging process, flip chipping the driver to the photonics die with tightly pitched bumps. It’s developing the technology with some heavyweight partners in communication and network applications within the French state-supported IRT Nanoelec Program under the “Programme Investissements d’Avenir”.

Aurrion takes a somewhat similar approach, building the waveguides and passive optical components directly on the silicon wafer, and then bonding on unprocessed chiplets of higher performance compound semiconductor material for the optical lasers, modulators and photodiodes. The chiplets don’t need to be precisely aligned on the waveguides, as they are etched in the desired patterns in the process flow that follows. Tooling for the die-to-wafer placement and low-temperature bonding have become more and more available from the MEMS and wafer-level –packaging world, which often require redistribution of chips on to a different wafer for packaging. “Leveraging the IC infrastructure allows scaling of III-V-based optical devices such as lasers and modulators up to very large arrays,” says Eric Hall, VP of Business Development at Aurrion, who also will speak.

It remains a challenge for efficient production that the optical fibers still often require active alignment with the photonic chip, but the necessary industry infrastructure for some sort of passive and standard connection solution may be starting to appear. Menezo suggests Intel’s cooperative development with fiber supplier Corning could be a first step, using silicon-photonics circuits and multi-mode fiber optimized at 1310nm to extend the reach to 430m at 25Gbps, compared to the 100m of standard VCSEL-based solutions. Another contribution to the developing infrastructure Leti’s porting its photonics library from its 200mm R&D line to its joint 300mm facility with STMicroelectronics. “It’s reassuring for commercialization that a path is now being opened to a production foundry,” she notes.

“Telecomm applications will be first, since they can afford the active alignment,” suggests Menezo, noting that commercial transmitters and receivers will likely start coming out late this year and next. “Shorter-reach applications will take a little longer, but with its competitive advantages of increased bandwidth density over increased transmission reach, and high volume production capacity, silicon photonics will likely replace electronics there in the five to eight year term.”

These speakers will be joined by Jean Trewhella from IBM, John Cunningham from Oracle, Eric Hall from Aurrion, and Peter de Dobbelaere from Luxtera to discuss recent progress in silicon photonics at SEMICON West, July 8-10, in San Francisco.

Paula Doe is technology director at SEMI.

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