Manufacturing Bits: Sept. 23

IEDM preview–Intel’s electrochemical capacitor; nanowire memory; FDSOI.


The annual IEEE International Electron Devices Meeting (IEDM) will take place in San Francisco from Dec. 15-17. As usual, there will be presentations on the latest technologies in a number of fields, such as semiconductors, bio‐sensors, energy harvesting, power devices, sensors, magnetics, spintronics, two-dimensional electronics, among others. Here’s just some of the papers that will be presented at the event:

Intel’s electrochemical capacitor
In some storage applications, capacitors have some advantages over batteries. Capacitors can capture energy at high rates and lower voltages and don’t require chemical reactions.

At IEDM, Intel will describe electrochemical capacitors based on porous-silicon (P-Si) nanostructures. The devices were fabricated using conventional silicon technology. This, in turn, enables them to be integrated on a single die with CMOS circuits, sensors and silicon solar cells.

SEMM shows a tapered porous-silicon nanostructure created by changing the current density during etching. (Source: Intel)

SEM shows a tapered porous-silicon nanostructure created by changing the current density during etching. (Source: Intel)

Using atomic layer deposition to coat the films, the structures demonstrated a high capacitance of 3 milliFarads/cm2. In the lab, Intel has built some porous-silicon electrochemical capacitors, which had a TiN coating. The structures exhibited a stable capacitance even after 1,000 cycles at 50 mV/sec.

By controlling various etch conditions, it is possible to vary the porous-silicon structures, according to Intel. In a SEM, Intel will show cross-sectional images of carbonized porous-silicon deposited at 500ºC and then at 720ºC with acetylene gas. Researchers will show images of the top of the porous-silicon region before and after stop-flow ALD TiN deposition. “The pore walls get thicker but the overall pore structure doesn’t change,” according to Intel.

New memory types
Phase-change memory, or PRAM, has been the subject of R&D for decades. Phase-change works by the rapid heating of a chalcogenide material, which shifts it between its crystalline and amorphous states.

At IEDM, researchers from the LEAP project will discuss a new type of PRAM, dubbed “topological-switching random-access memory,” or TRAM. “It stores data according to the movement of germanium (Ge) atoms in the material’s GeTe/Sb2Te3 crystal superlattice,” according to researchers. “It requires much less programming energy than the traditional chalcogenide-based PRAM to change states (as little as 1/20th).”

Researchers built TRAM devices that operated with a set/reset current as low as 55 µA. They also fabricated superlattices with 6nm-thick Sb2Te3 layers and others with composite bottom layers.

Meanwhile, flexible memories are generating steam. But to date, the devices have large feature sizes and poor performance, due to the limited fabrication methods for plastic substrates.

To solve the problem, KAIST will describe a process that involves transferring single-crystal silicon nanowire gate-all-around (GAA) SONOS memory devices onto a plastic substrate. Researchers demonstrated equivalent erasing speeds, retention and endurance characteristics (>104 program/erase cycles) before and after the transfer onto plastic.

Photo of a GAA SONOS FETs on an SOI wafer. (Source: KAIST)

Photo of a GAA SONOS FETs on an SOI wafer. (Source: KAIST)

“The transfer process begins with a protective layer coating on the GAA SONOS devices, followed by their attachment to a temporary handle wafer. The backside is thinned until a buried oxide (BOX) layer is exposed,” according to researchers. “The BOX layer acts as an etch stop layer for the silicon. The remaining ultrathin (~1 μm) film layer consisting of the GAA SONOS devices is transferred onto a flexible film, followed by the removal of the temporary handler and the protection layer.”

Here comes FDSOI
In a paper at IEDM, IBM and STMicroelectronics will discuss the implementation of strained fully-depleted silicon-on-insulator (FDSOI) technology for devices at 10nm. Researchers will discuss advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE and higher body factor.

IBM and ST will also demonstrate strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. “With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 μA/μm for NFET at Ioff=1 nA/um,” according to researchers. “And with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 μA/μm at Ioff=1 nA/um.”

And in a separate paper, CEA-LETI will describe the integration of dual channels in sub-15nm, CMOS nanowire devices. The devices feature uniaxially compressively strained SiGe PFETs with a gate shaped like the Greek letter omega for tight control of electrostatics in the channel.

TEM image of omega-gate CMOS nanowire transistor with a diameter of 12nm and gate length of 15nm. (Source: CEA-LETI)

TEM image of omega-gate CMOS nanowire transistor with a diameter of 12nm and gate length of 15nm. (Source: CEA-LETI)

They are co-integrated with silicon NFETs using a CMOS SOI-compatible process. Device dimensions are scaled to sub-15nm gate lengths, and nanowire widths are as narrow as 7nm. Ring oscillators with 80 stages were built that demonstrated a 50% reduction in delay.

More stuff
In the future, CMOS image sensors may run out of gas. This is because the two critical parts of the device–the photodetectors and signal processors–are in the same plane. The pixels must time-share a signal processor, thereby hampering the overall speed of the device, according to NHK.

At IEDM, NHK will describe a new technology in a paper, entitled: “Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers.” The parallel-processing technology, dubbed “pixel-parallel” processing, is a scheme in which each pixel has its own signal processor, according to researchers.

Researchers devised a 64-pixel prototype sensor. It captured video images and had a dynamic range of >80 dB, with the potential to be increased to >100 dB. In the device, the photodetectors and signal processors were built in stacked layers. The layers were bonded with damascene gold electrodes. This, in turn, provided each pixel with analog-to-digital conversion and a pulse frequency output.