IC Architectures Shift As OEMs Narrow Their Focus

By Ed Sperling - 03 Oct, 2022 - Comments: 0

Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they're expected to do, and how quickly they're supposed to do it. In the past, tradeoffs between performance, power, and cost were defined mostly by large OEMs within the confines of an industry-wide scaling roadmap. Ch... » read more

10 Questions: Handel Jones

By Ed Sperling - 20 Sep, 2022 - Comments: 0

Handel Jones, CEO of International Business Strategies and author of a new book, "When AI Rules The World," sat down with Semiconductor Engineering to talk about the growth and impact of AI. What follows are excerpts of that conversation. SE: What do you see as the impact of AI on semiconductors? Jones: The fact that you have a 5G smart phone is because of AI. Steve Jobs changed the smart... » read more

Chasing The Next Level Of Productivity

By Frank Schirrmeister - 25 Aug, 2022 - Comments: 0

The keynotes at the recent Design Automation Conference (DAC) gave some great insights into the direction of semiconductor technology and chip and system design. For the first time in a long time, my family members and friends have gained awareness of the importance of semiconductors and electronic design automation. I think this means it is also time to look back on where productivity improvem... » read more

Machine Learning-Driven Full-Flow Chip Design Automation

By Cadence - 24 Aug, 2022 - Comments: 0

To enable the semiconductor industry to continue growing, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning computer science, the next chip design automation revolution is now possible. The Cadence® Cerebrus™ Intelligent Chip Explorer utilizes both of these technologies, based o... » read more

Autonomous Design Automation: How Far Are We?

By Frank Schirrmeister - 24 Mar, 2022 - Comments: 0

The year is 2009, during the Design Automation Conference (DAC) at a press dinner in a posh little restaurant in San Francisco’s Civic Center. About two glasses of red wine in, one of the journalists challenges the table: “So, how far away are we from the black box that we feed with our design requirements and it produces the design that we send to the foundry?” We discussed all the indus... » read more

Does EDA Sell Fear?

By Brian Bailey - 24 Feb, 2022 - Comments: 3

I worked in the EDA industry for over 30 years and a common lament I heard was that the EDA industry survived by selling fear. Your new chip will fail if you do not buy the latest tool offering. There always seemed to be a natural dislike for the EDA industry and many users thought the industry overcharged and was unable to innovate. I never quite understood the reasoning. A recent comment, ... » read more

Spreadsheets: Still Valuable, But More Limited

By Brian Bailey - 10 Feb, 2022 - Comments: 1

Spreadsheets have been an invaluable engineering tool for many aspects of semiconductor design and verification, but their inability to handle complexity is squeezing them out of an increasing number of applications. This is raising questions about whether they still have a role, and if so, how large that role will be. There are two sides to this issue. On one side are the users who see them... » read more

The Importance Of Layering Data

By Ed Sperling - 11 Jan, 2022 - Comments: 0

The chip industry generates enormous quantities of data, from design through manufacturing, but much of it is unavailable or incomplete. And even when and where it is available, it is frequently under-utilized. While there has been much work done in terms of establishing traceability and data formats, the cross-pollination of data between companies and between equipment makers at various pro... » read more

Raising The Bar With The Next Generation Of AI For Chip Design

By Synopsys - 22 Nov, 2021 - Comments: 0

The semiconductor industry is enjoying renewed growth despite chip shortages plaguing everything from cars to kitchen appliances. But while the chips themselves continue to get faster and smarter, the chip design process itself hasn’t changed that much in 20+ years. It typically takes 2-3 years to design a chip with a large engineering team and tens or hundreds of millions of dollars to get a... » read more

Debug Solutions For Designers Accelerate Time To Verification

By Neil Hand - 28 Oct, 2021 - Comments: 0

Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars. Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Rese... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?