Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization


A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

CEO Outlook: Chiplets, Data Management, And Reliability


Semiconductor Engineering sat down to talk about changes in chip design with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business Unit; Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight; ... » read more

Auto Industry Relationships Re-Form, But Differently


The automotive industry is in the midst of rapid change on many fronts. OEMs are exploring new functions and features to add to their vehicles, including chiplets, electrification, autonomous features, as well as new vehicle architectures that will determine how vehicles are going to be designed from the foundation up. But all of this is dependent on the relationships between all of the ecosyst... » read more

Framework To Compile Quantum Programs Onto Chiplets (UCSB, Cisco)


A technical paper titled "Compilation for Quantum Computing on Chiplets" was published by researchers at UC Santa Barbara and Cisco Quantum Lab. Abstract: "Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalability and modularity. However, as the computing scale increases, communication between qubits w... » read more

Chiplet Planning Kicks Into High Gear


Chiplets are beginning to impact chip design, even though they are not yet mainstream and no commercial marketplace exists for this kind of hardened IP. There are ongoing discussions about silicon lifecycle management, the best way to characterize and connect these devices, and how to deal with such issues as uneven aging and thermal mismatch. In addition, a big effort is underway to improve... » read more

IP Becoming More Complex, More Costly


Success in the semiconductor intellectual property (IP) market requires more than a good bit of RTL. New advances mandate a complete design, implementation, and verification team, which limits the number of companies competing in this market. What constitutes an IP block has changed significantly since the concept was first introduced in the 1990s. What was initially just a piece of RTL (reg... » read more

Automotive Relationships Shifting With Chiplets


The automotive industry is in the midst of a tremendous and rapid change on many fronts. OEMs are exploring new functions and features to add to their vehicles, including chiplets, electrification, autonomous features, as well as new vehicle architectures that will determine how vehicles are going to be designed from the foundation up. All of this is dependent on the relationships between all o... » read more

Chips Getting More Secure, But Not Quickly Enough


Experts at the Table: Semiconductor Engineering sat down to talk about the impact of heterogeneous integration, more advanced RISC-V designs, and a growing awareness of security threats, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketin... » read more

From Known Good Die To Known Good System With UCIe IP


Multi-die systems are made up of several specialized functional dies (or chiplets) that are assembled in the same package to create the complete system. Multi-die systems have recently emerged as a solution to overcome the slowing down of Moore’s law by providing a path to scaling functionality in the packaged chip in a way that is manufacturable with good yield. Additionally, multi-die sy... » read more

Optimizing Scan Test For Complex ICs


As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability. In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifec... » read more

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