Defect Challenges Grow At The Wafer Edge


Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

Shaping The Future Of Automotive Safety With V2X


In recent years, the automotive industry has witnessed a technological evolution that promises to redefine road safety and driving experiences. At the heart of this advancement is V2X technology, which stands for "vehicle-to-everything." This innovation allows vehicles to communicate with each other and their surroundings, enhancing road safety and efficiency. Understanding these cutting-edge d... » read more

Scalable Chiplet System for LLM Training, Finetuning and Reduced DRAM Accesses (Tsinghua University)


A new technical paper titled "Hecaton: Training and Finetuning Large Language Models with Scalable Chiplet Systems" was published by researchers at Tsinghua University. Abstract "Large Language Models (LLMs) have achieved remarkable success in various fields, but their training and finetuning require massive computation and memory, necessitating parallelism which introduces heavy communicat... » read more

New AI Processors Architectures Balance Speed With Efficiency


Leading AI systems designs are migrating away from building the fastest AI processor possible, adopting a more balanced approach that involves highly specialized, heterogeneous compute elements, faster data movement, and significantly lower power. Part of this shift revolves around the adoption of chiplets in 2.5D/3.5D packages, which enable greater customization for different workloads and ... » read more

A New Generation Of 7400 Socket


When I was 18, and just been accepted at Brunel University in West London to start my undergraduate degree in electrical and electronic engineering, I sent off a letter to Texas Instruments telling them about the journey ahead of me and asked if they could they send me a copy of their TTL Data Book. A few weeks later a package arrived and there it was. This incredible brown/orange book, thicker... » read more

Defining The Chiplet Socket


Experts At The Table: The semiconductor industry has been buzzing with the possibilities surrounding chiplets, but so far this packaging technology has been confined to large semiconductor companies that are vertically integrated. The industry has been attempting to open this up to a broader group of people. To work out what this means for chiplets, and what standardization will be required, Se... » read more

Chiplets and the Early Adopter’s Dilemma


Early adopters of a new technology often face a serious dilemma. On one hand, moving early means exploiting the most aggressive new technology available. But on the other hand, making early technology decisions can lock a product line into a path that will later become uncompetitive—either a single-vendor solution that can’t guarantee continuity of supply, or a roadmap that can’t shift an... » read more

3.5D: The Great Compromise


The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Joint Interdisciplinary Work To Enable Novel, Industry-Ready Chiplet Solutions


Fraunhofer is going to establish the Chiplet Center of Excellence (CCoE), which is a unique research activity based on Fraunhofer‘s long experience and broad research portfolio in design, implementation and test of 2.5 and 3D integrated electronic systems. The Center aims at establishing a common understanding among the partners and at creating a suitable chiplet development methodology. This... » read more

Metrology And Inspection For The Chiplet Era


New developments and innovations in metrology and inspection will enable chipmakers to identify and address defects faster and with greater accuracy than ever before, all of which will be required at future process nodes and in densely packed assemblies of chiplets. These advances will affect both front-end and back-end processes, providing increased precision and efficiency, combined with a... » read more

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