tag: chiplets

Breakthrough Thin GaN Chiplet Technology
By Han Wui Then - 16 Apr, 2026 - Comments: 0

Researchers at Intel Foundry have demonstrated a gallium nitride (GaN) chiplet technology built on 300 mm GaN-on-silicon wafers, marking a significant leap forward in semiconductor design. Presented at the 2025 IEEE International Electron Devices Meeting (IEDM), this work tackles one of the most pressing challenges in modern computing: how to deliver more power, speed, and efficiency in an incr... » read more

Why More CPUs Are Needed For Agentic AI
By Ed Sperling - 15 Apr, 2026 - Comments: 0

The shift from generative AI to agentic AI will significantly increase the amount of compute power needed in data centers. Queries to search for and analyze data from multiple sources will be performed simultaneously by agents and without human intervention, rather than a single request from a live person. Jeff Defilippi, senior director of product management at Arm, talks about the impact of r... » read more

Developing A Security Framework For Chiplet-Based Systems
By Berardino Carnevale - 02 Apr, 2026 - Comments: 0

In a previous blog, From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm, we discussed why chiplets change the game from a security perspective, and why security must be addressed at a platform-level in a chiplet-based system. In a monolithic SoC, device identity is often anchored in a single root of trust that owns key material and policy. In a chiplet platform, every security... » read more

Preparing For The Multiphysics Future of 3D ICs
By Siemens EDA - 01 Apr, 2026 - Comments: 0

3D integrated circuits (3D ICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3D ICs are poised to transform the landscape of electronic devices. However, with 3D ICs come new design and verification challenges that must be addressed to ensure success... » read more

Advanced Packaging Limits Come Into Focus
By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "Link Quality Aware Pathfinding for Chiplet Interconnects," was published by researchers at UCLA. Abstract "As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER ... » read more

Improving Yield Through Shared Data
By Ed Sperling - 11 Mar, 2026 - Comments: 0

Increasing complexity due to advanced packaging, multi-die assemblies, and more devices under test is having an impact on yield, which in turn slows time to market and impacts overall chip costs. What's needed is a way to share data that previously was siloed by chipmakers, fabs, and OSATs. Jayant D'Souza, technical product director at Siemens EDA, talks about the underlying drivers for sharing... » read more

Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs
By Yervant Zorian - 10 Mar, 2026 - Comments: 0

By Yervant Zorian and Sandeep Kumar Goel Anyone who follows the semiconductor industry knows that the accelerating performance, scale and energy efficiency demands of the AI revolution are outpacing the advances achievable by simply pushing the chip performance of monolithic, single-die designs. Multi-die design using 2.5D and 3D technologies has emerged as a necessity to keep the pace of in... » read more

How AI Is Changing Computing And Why Testing Is Critical
By Jeorge Hurtarte - 10 Mar, 2026 - Comments: 0

Artificial intelligence (AI) is transforming industries, enhancing our daily lives, and improving efficiency and decision-making, but its need for compute processing power is growing at an astonishing rate, doubling every three months (Figure 1). To maintain this pace, the semiconductor industry is moving beyond traditional chip development – it has entered the era of heterogeneous chiplets i... » read more

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