tag: chiplets

Router-in-a-Package Design Combining HBM4, Chiplets and In-Package Optics (Technion, Berkeley, UCSD)
By Technical Paper Link - 18 Feb, 2026 - Comments: 0

A new technical paper "Scaling Routers with In-Package Optics and High-Bandwidth Memories" was posted by researchers at Technion, UC Berkeley and UC San Diego. Abstract "This paper aims to apply two major scaling transformations from the computing packaging industry to internet routers: the heterogeneous integration of high-bandwidth memories (HBMs) and chiplets, as well as in-package optic... » read more

How Siemens Symphony Pro Enabled AnalogPort To Verify Complex Chip Interfaces
By Siemens EDA - 13 Feb, 2026 - Comments: 0

The semiconductor industry's shift toward chiplet-based architectures has created significant mixed-signal verification challenges for high-speed die-to-die interconnects. Traditional verification approaches force difficult trade-offs: Digital mixed-signal (DMS) flows sacrifice analog fidelity, while Analog mixed-signal (AMS) flows struggle with scalability and manual overhead. This paper detai... » read more

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
By Ann Mutschler - 12 Feb, 2026 - Comments: 1

Key Takeaways • Chiplets and 3D-IC architectures add new thermal-mechanical stresses that can affect the reliability of entire systems. • As chiplets are assembled into packages, defectivity targets become more stringent for each component in a system. • Traditional silos are breaking down, forcing design teams to address issues such as materials choices that previously were handled by... » read more

UCIe’s Major Technical Components Are Now In Place
By Bryon Moyer - 12 Feb, 2026 - Comments: 0

Key Takeaways UCIe 3.0 doubles bandwidth and enhances manageability, addressing new use cases and following an annual update cycle since 2023. The growing demand for chiplet-based architectures in AI data centers is driven by the limitations of monolithic chips, making inter-chiplet communication and connectivity crucial. While UCIe was initially seen as feature-heavy, many of its ma... » read more

Catching Critical Defects In TSVs And Stacked Chips
By Laura Peters - 10 Feb, 2026 - Comments: 0

Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Six 3D-IC Design Trends That Secure The AI Era
By Pratyush Kamal - 05 Feb, 2026 - Comments: 0

By Pratyush Kamal and Todd Burkholder Greater functionality, performance, and speed are in great demand in pervasive computing, RF, and automotive electronic systems, as well as most everything else. Complexity continues to skyrocket, leading many to say we are officially in the post-Moore’s Law world. In his seminal 1965 paper, “Cramming more components onto integrated circuits,�... » read more

From Monolithic SoCs To Chiplets: A New Hardware Security Paradigm
By Berardino Carnevale - 05 Feb, 2026 - Comments: 0

Chiplet architectures are quickly becoming the dominant approach for building scalable, heterogeneous SoCs. By disaggregating a monolithic die into multiple interoperable chiplets, silicon designers gain flexibility in process node choices, reuse of proven functions, and faster time-to-market. At the same time, disaggregation breaks one of the most fundamental assumptions in traditional SoC sec... » read more

A Manufacturing Approach That Brings Diamond Quantum Photonics Closer To Industrial Production (MIT, KAUST et al.)
By Technical Paper Link - 02 Feb, 2026 - Comments: 0

"Foundry-Enabled Patterning of Diamond Quantum Microchiplets for Scalable Quantum Photonics" was published by researchers at MIT, KAUST, PhotonFoundries and MITRE. Abstract "Quantum technologies promise secure communication networks and powerful new forms of information processing, but building these systems at scale remains a major challenge. Diamond is an especially attractive material fo... » read more

Chiplet Fundamentals For Engineers: eBook
By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

How The EDA Industry Will Evolve In 2026
By Niels Faché - 29 Jan, 2026 - Comments: 0

AI will continue to impact every facet of the EDA industry. Pressure will mount in 2026 on design teams to drive productivity gains while technical complexity continues to escalate. This will reshape how teams work and the tools they use. Success will be determined by balancing the trade-offs between integrated platforms and best-of-breed toolchains and developing talent internally rather than ... » read more

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