tag: chiplets

The Next Wave Of Consolidation
By Ed Sperling - 28 Sep, 2020 - Comments: 0

End markets and technologies are changing, stock prices are up, and interest rates are down. Those are the necessary ingredients for acquisition binging. So why isn't much happening? The answer is that more industry consolidation is ahead, but it's all happening more slowly than the economics would suggest. Some of the reasons are obvious, others less so. The big delay is the COVID-19 pa... » read more

How Secure Is The Package?
By Ed Sperling - 17 Sep, 2020 - Comments: 1

Advanced packaging is a viable way of extending the benefits of Moore's Law without the excessive cost of shrinking everything to fit on a single die, but it also raises some issues about security for which there are no clear answers at the moment. OSATs and foundries have been working the kinks out of how to put the pieces together in the most cost-effective and reliable way for the better ... » read more

Momentum Builds For Advanced Packaging
By Mark LaPedus - 17 Sep, 2020 - Comments: 0

The semiconductor industry is stepping up its efforts in advanced packaging, an approach that is becoming more widespread with new and complex chip designs. Foundries, OSATs and others are rolling out the next wave of advanced packaging technologies, such as 2.5D/3D, chiplets and fan-out, and they are developing more exotic packaging technologies that promise to improve performance, reduce p... » read more

Are Chips Getting More Reliable?
By Ed Sperling - 08 Sep, 2020 - Comments: 0

The semiconductor industry is making huge progress in understanding the causes and telltale signs of circuit aging and irregular behavior. But are devices actually getting more reliable? The answer depends on a number of factors, none of which is easily measured. To be sure, circuits are much better designed and inspected than in the past, and the individual components are printed more accur... » read more

Interconnects Emerge As Key Concern For Performance
By Ed Sperling - 03 Sep, 2020 - Comments: 0

Interconnects are becoming increasingly challenging to design, implement and test as the amount of data skyrockets and the ability to move that data through denser arrays of compute elements and memories becomes more difficult. The idea of an interconnect is rather simple, but ask two people what constitutes an interconnect and you're likely to get very different answers. Interconnects are e... » read more

Moore’s Law Enters The 4th Dimension
By Ed Sperling - 21 Aug, 2020 - Comments: 5

The basic idea that more transistors are better hasn't changed in more than half a century. In fact, the overriding theme of a number of semiconductor conferences this month is that we will never have enough compute capability or storage capacity. In the past, when the number of transistors in a given area actually did double every 18 to 24 months, increasing density per square millimeter fo... » read more

Monitoring Chips After Manufacturing
By Brian Bailey - 19 Aug, 2020 - Comments: 2

New regulations and variability of advanced process nodes are forcing chip designers to insert additional capabilities in silicon to help with comprehension, debug, analytics, safety, security, and design optimization. The impact of this will be far-reaching as the industry discusses what capabilities can be shared between these divergent tasks, the amount of silicon area to dedicate to it, ... » read more

Redefining The Power Delivery Network
By Brian Bailey - 13 Aug, 2020 - Comments: 3

Reliably getting power around a package containing multiple dies, potentially coming from multiple sources, or implemented in diverse technologies, is becoming much more difficult. The tools and needed to do this in an optimized manner are not all there today. Nevertheless, the industry is confident that we can get there. For a single die, the problem has evolved slowly over time. "For a ... » read more

Preparing For A Barrage Of Physical Effects
By Ann Mutschler - 13 Aug, 2020 - Comments: 0

Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

Power And Performance Optimization At 7/5/3nm
By Ed Sperling - 13 Aug, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

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