No More Easy IP Money

By Brian Bailey - 14 Jul, 2016 - Comments: 2

The semiconductor intellectual property ([getkc id="43" kc_name="IP"]) industry is two decades old, but questions are still being asked about what's wrong with it and what needs to be fixed. Normally these kinds of issues are reserved for fast-moving, young industries, not one that is the backbone of semiconductors. Design reuse has become an indispensable part of the design of nearly all el... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together

By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

Bridging the IP Divide

By Brian Bailey - 18 May, 2016 - Comments: 1

IP reuse enabled greater efficiency in the creation of large, complex SoCs, but even after 20 years there are few tools to bridge the divide between the IP provider and the IP user. The problem is that there is an implicit fuzzy contract describing how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to... » read more

Bridging The IP Divide

By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

HW Vs. SW: Who’s Leading Whom?

By Brian Bailey - 29 Oct, 2015 - Comments: 6

In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Blog Review: Sept. 9

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

The Next Big Threat: Manufacturing

By Ed Sperling - 23 Jan, 2014 - Comments: 0

The business adage that you’re only as good as your partners should be a core principle of doing business when it comes to security. But with a complex SoC you don’t always know all your partners, who financed them—or worse, who else they’re working with or working for. Consider this scenario: A band of sophisticated thieves grinds off the top of an SoC package, inserts probes to map... » read more

Industry Restructures Around Cost

By Ed Sperling - 19 Dec, 2013 - Comments: 1

Talk to any semiconductor executive these days about what’s next for their company and you’ll probably encounter the same perspective—cost will drive future design decisions. Dig a little further, however, and you’ll find no consistent strategy for reducing that cost. While the industry has three very viable solutions for improving the power and performance characteristics of SoCs—... » read more

Even Standard IP Isn’t Always Standard

By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Uncertainty Increases About What’s Next

By Ed Sperling - 24 Oct, 2013 - Comments: 0

Across the semiconductor industry, there is a lot of talk about what’s next. Lithography advances have stalled, NRE and mask costs are rising, and complexity is exploding. But unlike the 1 micron wall, which was supposed to be impenetrable, there is no single issue holding back progress. Instead, there are lots of them, most with pricey workarounds, but which together become more complicat... » read more

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No More Easy IP Money

DAC Day Three: UVM, Machine Learning And DFT Come Together

Bridging the IP Divide

Bridging The IP Divide

HW Vs. SW: Who’s Leading Whom?

Blog Review: Sept. 9

The Next Big Threat: Manufacturing

Industry Restructures Around Cost

Even Standard IP Isn’t Always Standard

Uncertainty Increases About What’s Next

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