tag: clock domain crossing

Choosing The Right Verification Technology For CDC-Clean RTL Signoff
By Cadence - 24 May, 2017 - Comments: 0

Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains. Clock domain crossing (CDC) signals, those which traverse these domains, are often subject to metastability effects that can cause functional errors. Traditional methods like RTL simulation or static timing analysis alone are not sufficient to verify correct data transfer across clock domains. As a result... » read more

Formal’s Roadmap
By Brian Bailey - 22 Nov, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Five Steps To Quality CDC Verification
By Mentor, a Siemens Business - 12 Oct, 2016 - Comments: 0

With the number of clock domains increasing in today's complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verifi... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Debug: Last Bastion Of Automation
By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Finding CDC Issues Before They Find You
By Aldec - 27 Jan, 2016 - Comments: 0

Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated. To read more, cl... » read more

Verification Grows Up
By Brian Bailey - 22 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down with a group of verification experts to see how much progress has been made in solving issues associated with the profession. Panelists included Mike Baird, president of Willamette HDL; Jin Zhang, VP marketing and customer relations for [getentity id="22147" comment="Oski Technology"], and Lauro Rizzatti, a marketing consultant and previously the general manag... » read more

Power Aware CDC Verification Of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
By Mentor, a Siemens Business - 09 Dec, 2015 - Comments: 0

Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic. We will discuss the effects of advanced low power design on CDC design and verification. This paper describes the new CDC issues caused by the addition of power control logic including isolation cells, retention cells, lev... » read more

The Problem With CDCs
By Louie De Luna - 24 Nov, 2015 - Comments: 0

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with multiple asynchronous clocks which necessitates using advanced verification techniques targeting anomalies related to clock domain crossings (CDCs). Typical electronic design automation (EDA) tools f... » read more

The New Face Of Formal
By Brian Bailey - 29 Oct, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager of R&D in the verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphic... » read more

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