tag: clock domain crossing

Clock Domain Crossings in the FPGA World
By Aldec - 30 Jan, 2019 - Comments: 0

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

The Impact of Domain Crossing on Safety
By Brian Bailey - 31 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

So Many Waivers Hiding Issues
By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

Domain Crossing Nightmares
By Brian Bailey - 27 Sep, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

UPF-Aware Clock-Domain Crossing
By Ed Sperling - 29 Aug, 2018 - Comments: 0

Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters. https://youtu.be/HwRe9DHLfmg » read more

Raising The Bar On Flat CDC Verification With Hierarchical Data Models
By Ashish Hari - 28 Jun, 2018 - Comments: 0

By Ashish Hari, Aditya Vij, and Ping Yeung Traditionally, clock domain crossing (CDC) verification at the SoC level has relied on flat simulation runs. But flat CDC verification has run out of gas. Largely because of the increase in the number of asynchronous clocks in larger, faster, more complex designs. Flat CDC runs are too performance intensive, time-consuming, and result in high noise.... » read more

Comprehensive CDC Verification Using Advanced Hierarchical Data Models
By Mentor, a Siemens Business - 27 Jun, 2018 - Comments: 0

In this paper, we describe the hierarchical data model (HDM), which is a performance efficient alternative to the traditional flat CDC verification flow. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly re-used across releases and across designs wherever the IP i... » read more

The Week In Review: Design
By Jesse Allen - 22 Jun, 2018 - Comments: 0

Tools Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, a... » read more

Respecting Reset
By Brian Bailey - 25 May, 2017 - Comments: 0

Resets are a necessary part of all synchronous designs because they allow them to be brought into a known state. However, such a simple process can lead to many problems within an [getkc id="81" kc_name="SoC"]. No longer can reset be considered a simple operation when power initially is applied to a circuit. Instead, the design of reset has many implications on cost, area and routability, a... » read more

Choosing The Right Verification Technology For CDC-Clean RTL Signoff
By Cadence - 24 May, 2017 - Comments: 0

Modern system-on-chip (SoC) designs typically contain multiple asynchronous clock domains. Clock domain crossing (CDC) signals, those which traverse these domains, are often subject to metastability effects that can cause functional errors. Traditional methods like RTL simulation or static timing analysis alone are not sufficient to verify correct data transfer across clock domains. As a result... » read more

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