The Week In Review: Design

New tools: power analysis, physical verification, CDC, and more; interconnects for AI SoCs; CCIX 1.0.


Synopsys revealed a power analysis solution for early SoC design as well as signoff-accurate power and reliability closure. PrimePower has reliability as a major focus, expanding power and reliability signoff and ECO closure capabilities from physical awareness to cell electromigration effects. Supported power types include peak power, average power, clock network power, leakage power, and multivoltage power. It has a native interface with the company’s emulation system and static timing analysis and signoff tool.

Mentor launched a new physical verification tool, Calibre RealTime Digital, targeting  the full-chip and block-level digital market. The tool works with place-and-route tools to make minor changes to fix violations discovered after full DRC runs then performing smaller and more localized DRC runs.

Real Intent debuted a new tool to debug clock domain crossing violations at the gate level netlist of digital designs. Verix PhyCDC targets the post-synthesis stage of SoC design and uses results from RTL CDC to identify incremental CDC paths and constraints to optimize the CDC analysis at gate level. It addresses malfunctions such as glitching on control signals, clock networks and data signal paths as well as incorrect optimization of clock synchronizer logic.

Synopsys released its latest emulation system, ZeBu Server 4. The system uses Xilinx Virtex UltraScale VU440 FPGAs containing 19 billion transistors and 5.4 million logic gates, and is scalable to designs over 19 billion gates. The company says it provides high performance with low power consumption and a small datacenter footprint.

Plunify uncorked the latest version of its timing closure tool, InTime, which introduces post-placement estimates analysis and supports multiple concurrent compilations in the cloud. Additionally, a new Plunify Cloud plugin capability for the Xilinx Vivado Design Suite allows for optimization of designs directly in the cloud if local resources and licenses aren’t sufficient.

OneSpin Solutions rolled out a Tool Qualification Kit for its automatic sequential equivalence checker for FPGAs to support the DO-254 safety standard. The kit includes tool qualification guidelines, tool documentation, quality assurance practices documentation and a compliant development processes certificate.

UltraSoC and Imperas are teaming up on a debug environment combining the companies’ embedded analytics and virtual platform technologies. The integrated design flow will see UltraSoC incorporating key elements of Imperas’ development environment into its tools offering.

NetSpeed Systems unveiled new interconnect IP targeted at AI-focused SoCs and accelerator ASICs. Orion AI can provide terabits of on-chip bandwidth as well as super-wide data paths with interfaces of up to 1024 bits, long bursts of up to 4K Bytes, and multicast and broadcast. The solution includes NetSpeed’s machine learning engine for optimizing SoC design.

Flex Logix announced new embedded FPGA cores optimized for 40nm to 180nm nodes. That need smaller arrays. The EFLX1K Logic and DSP cores use 10-20% less array/LUT because the interconnect network in the cores implement fewer switch levels for less expandability than the EFLX4K, which is targeted at 28nm and 16nm. The logic core has 368 inputs and 368 outputs with 900 LUT4 equivalent logic capacity, while the DSP core replaces some of the LUTs with DSPs. The logic and DSP cores can be mixed interchangeable in arrays up to at least 4×4 in size.

Arm and Samsung announced an embedded MRAM compiler offering which will be available on Samsung Foundry’s 28FDS (FDSOI) process technology. According to the companies, eMRAM can be integrated with as few as three additional masks, while eFlash requires greater than 12 additional masks at 40nm and below. Arm has successfully completed the first eMRAM IP test chip tapeout.

Arasan Chip Systems released SD Card UHS-II PHY IP for 12nm SoC designs compliant to the latest 4.1 Specification supporting speeds of up to 3.12 Gbps and can be enhanced to support the latest SD Card UHS-III PHY. The UHS-II PHY is silicon proven on TSMC 12nm.

The CCIX Consortium released the CCIX Base Specification 1.0, which defines a chip-to-chip interconnect for seamless data sharing between compute, accelerators and memory expansion devices with cache coherent shared virtual memory. The specification leverages the PCI Express 4.0 architecture and ecosystem while increasing the throughput to 25GT/s per lane and adding the ability to maintain cache coherency across devices from different providers.

Brian Krzanich has resigned as Intel CEO and a member of the board of directors. According to a statement from Intel, Krzanich violated the company’s non-fraternization policy, which applies to all managers. Chief Financial Officer Robert Swan will serve as interim chief executive officer. Swan has been Intel’s CFO since October 2016. He previously spent nine years as CFO of eBay.

Gary Smith EDA transferred its business operations to Pedestal Research, which will continue providing market research and consulting for the EDA, IoT, ESL, and IP markets under the leadership of Laurie Balch, formerly Chief Analyst at Gary Smith EDA.

Martin Barnasconi will receive the seventh annual Accellera Leadership Award, which honors him for dedication to the advancement of the SystemC ecosystem and growth of standards dissemination in Europe. “He led the development and release of the SystemC AMS standard in Accellera, successfully delivering it to the IEEE and chairing the efforts resulting in IEEE 1666.1. He spearheaded the expansion of DVCon into Europe, and is a co-founder of the successful SystemC Evolution Day,” said Lu Dai, Accellera Chair. Barnasconi is currently Technical Director System Design & Verification Methodologies at NXP.

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