tag: clock domain crossing

Effective Clock Domain Crossing Verification
By Rahul Chirania - 15 Oct, 2020 - Comments: 0

As chips grow ever larger and more complex, gate count and amount of embedded memory grow dramatically. The number of clock domains is also increasing steadily. Several dozen different clocks are common in today’s chips, with some designs having more than a thousand domains. There are several reasons for this explosion: Multiple external interfaces with distinct clock requirements Lic... » read more

Productivity Keeping Pace With Complexity
By Brian Bailey - 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

Eliminate Silicon Respins With Netlist CDC Verification
By Synopsys - 24 Jun, 2020 - Comments: 0

Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for advanced designs and complex flows, there is significant logic optimization during RTL synthesis as well as backend flows at the netlist stage. This mandates clock domain crossing verification a must for... » read more

Constraint-Based Verification Of Clock Domain Crossings
By Synopsys - 25 Mar, 2020 - Comments: 0

There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these factors mean more time spent in design, but they also have a major impact on verification. Since virtually all industry studies show verification time and effort growing faster than design, this impa... » read more

Fusing Implementation And Verification
By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

Shift Left Power-Aware Static Verification
By Himanshu Bhatt - 10 Oct, 2019 - Comments: 0

Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

Clock Domain Crossing Signoff Through Static-Formal-Simulation
By Sudeep Mondal - 22 Aug, 2019 - Comments: 0

By Sudeep Mondal and Sean O'Donohue Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain Crossing (CDC) analysis tools. Today, the majority of IP and SoC teams are focusing on “Structural CDC” analysis, which is important but not sufficient. Structural CDC analysis ensures that the d... » read more

Signoff-Compatible CDC
By Ed Sperling - 29 Jul, 2019 - Comments: 2

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools
By Chris Giles - 30 May, 2019 - Comments: 0

Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

Adding Order And Structure To Verification
By Brian Bailey - 30 May, 2019 - Comments: 0

You can't improve what you can't measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of individuals within an organization, which may affect their ability to adopt certain technologies, and it requires considerable attention. This is where concepts such as capability maturity models (CM... » read more

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