I Say ‘High’ [Performance], You Say ‘Low’ [Power]


“…You say ‘why’, and I say ‘I don’t know…’” Actually, I do know. Everybody loves a high-performance product. Even just hearing that a product is high-performance sets higher expectations than if the product is simply described as “fast” or “powerful.” When it comes to SoC design, “high-performance” refers to a set of designs that run at very high clock freque... » read more

The Problem With Clocks


The synchronous digital design paradigm has enabled us to design circuits that are well controlled, but that is only true if the clocks themselves are well controlled. While overdesign techniques ensured that to be the case in early ASIC development, designs today cannot afford such luxuries. As we strive for lower power and higher operating frequencies, the clock has become a critical desig... » read more

The Ultimate Shift Left


Floorplanning is becoming much more difficult due to a combination of factors—increased complexity of the power delivery network, lengthening of clock trees, rising levels of communication, and greater connectedness of [getkc id="81" kc_name="SoC"]s coupled with highly constrained routing resources. The goal of floorplanning is to determine optimal placement of blocks on a die. But connect... » read more

Making 2.5D, Fan-Outs Cheaper


Now that it has been shown to work, the race is on to make advanced [getkc id="27" kc_name="packaging"] more affordable. While device scaling could continue for another decade or more, the number of companies that can afford to develop SoCs at the leading edge will continue to decline. The question now being addressed is what can supplant it, supplement it, or redefine it. At the center o... » read more

SCREAMER: A Demonstrator Chip For Spectral Noise Optimization By Clock Latency Scheduling


This paper outlines the design and measurement of a 130 nm test chip named SCREAMER for reducing the digital switching noise in synchronous circuits. Clock latency scheduling has been investigated as a means to optimize switching noise in the frequency domain through PDN simulation. Integrated in parallel on the chip are four instances of a test design, each addressing a distinct strategy of cl... » read more

The Trouble With Clock Trees


By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more