Making 2.5D, Fan-Outs Cheaper

By Ed Sperling - 17 Nov, 2016 - Comments: 2

Now that it has been shown to work, the race is on to make advanced [getkc id="27" kc_name="packaging"] more affordable. While device scaling could continue for another decade or more, the number of companies that can afford to develop SoCs at the leading edge will continue to decline. The question now being addressed is what can supplant it, supplement it, or redefine it. At the center o... » read more

SCREAMER: A Demonstrator Chip For Spectral Noise Optimization By Clock Latency Scheduling

By Teklatech - 13 Apr, 2016 - Comments: 0

This paper outlines the design and measurement of a 130 nm test chip named SCREAMER for reducing the digital switching noise in synchronous circuits. Clock latency scheduling has been investigated as a means to optimize switching noise in the frequency domain through PDN simulation. Integrated in parallel on the chip are four instances of a test design, each addressing a distinct strategy of cl... » read more

The Trouble With Clock Trees

By Arvind Narayanan - 11 Oct, 2012 - Comments: 0

By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more

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3.5D: The Great Compromise

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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tag: clock tree synthesis

Making 2.5D, Fan-Outs Cheaper

SCREAMER: A Demonstrator Chip For Spectral Noise Optimization By Clock Latency Scheduling

The Trouble With Clock Trees