tag: CMP

Silicon Photonics: Solving Process Variation And Manufacturing Challenges
By Sandy Wen - 17 Aug, 2017 - Comments: 0

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur i... » read more

ECO Fill Can Rescue Your SoC Tapeout Schedule
By Vikas Gupta - 16 Feb, 2017 - Comments: 0

By Vikas Gupta and Bhavani Prasad Integrated circuit (IC) design and manufacturing is one of the most challenging engineering industries. As soon as a design engineer gets into “the groove” and feels comfortable taping out in a particular technology node, the next technology node shrink is already there to pose a new and greater set of challenges. While it almost goes without saying that... » read more

Politics And (Low) Power
By Ed Sperling - 10 Nov, 2016 - Comments: 4

This week the entire semiconductor market woke up with a severe political hangover. Aside from the initial shock of the election results themselves, the winning platform of "America First" could have far-reaching implications for an industry that has spent decades optimizing a global supply chain the way it has finely tuned other processes to reduce the cost per transistor. There are many un... » read more

Creating An Accurate FEOL CMP Model
By Jeff Wilson - 20 Oct, 2016 - Comments: 0

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid For decades, semiconductor manufacturers have used chemical-mechanical polishing (CMP) as the primary technique for the smoothing and leveling (planarization) of dielectrics and metal layers. CMP modeling allows  design and manufacturing teams to find and fix potential planarization issues before the actual CMP process is applied to a ... » read more

A Novel Approach To Dummy Fill For Analog Designs Using Calibre SmartFill
By Mentor, a Siemens Business - 19 Oct, 2016 - Comments: 0

With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

200mm Equipment Shortfall
By Mark LaPedus - 21 Jul, 2016 - Comments: 0

A surge in demand for consumer electronics, communications ICs, sensors and other products has created a shortage in 200mm fab capacity that shows no signs of abating. None of these chips need to be manufactured using the most advanced processes, and there have been enough tweaks to processes at established nodes to eke even more out of existing processes. But that has left chipmakers strugg... » read more

Increasing Challenges At Advanced Nodes
By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Déjà Vu For CMP Modeling?
By Jeff Wilson - 17 Sep, 2015 - Comments: 0

One definition of design for manufacturing (DFM) is providing knowledge about the impact of the manufacturing process on a design layout to the designers, so they can use that information to improve the robustness, reliability, or yield of their design before tapeout. Essentially, DFM is about designers taking ownership of the full “lifecycle” of a design, and going beyond the required desi... » read more

Still Searching For Rare Earths
By Mark LaPedus - 20 Aug, 2015 - Comments: 1

There is both good and bad news for buyers of rare earths. The good news: It’s a buyers’ market. Prices for rare earths remain depressed amid a glut in the marketplace. The bad news: The supplier base is shaky. China still accounts for 85% of the world’s total production of rare earths, but most Chinese suppliers are operating at a loss. And two of the main non-Chinese suppliers, M... » read more

It’s a Materials World, With Positive Forecast
By SEMI - 23 Jul, 2015 - Comments: 0

By Michael Fury What’s the latest in materials forecasts for ALD/CVD precursors, CMP consumables, electronic gases, silicon wafers and sputtering targets? Techcet gives us an update. Metal Gate and Electrode Precursors to Double in Five Years Use of front-end Ta and W metal gate and Hf gate dielectric precursors will grow over 2.5x by 2020, according to a new report from Techcet, “20... » read more

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