tag: CMP

Surprises At SEMICON West
By Joanne Itow - 23 Jul, 2015 - Comments: 0

As companies such as TSMC and Intel spend less on capital expenditures this year, expectations for SEMICON West 2015 were pretty bleak. I thought I’d have fewer appointments and nothing to really write home about. Au contraire. Although traffic on the show floor was nothing compared to events like CES, there are three things that are driving growth and excitement at semiconductor equipment... » read more

Foundries Expand Planar Efforts
By Mark LaPedus - 18 Jun, 2015 - Comments: 0

Competition is heating up in the leading-edge foundry business, as vendors begin to ramp up their new 16nm/14nm finFET processes. But that’s not the only action in the foundry arena. They are also expanding their efforts in the leading-edge planar market by rolling out new 28nm and 22nm processes. On one front, TSMC is offering new 28nm variants, based on bulk CMOS technology. And on an... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 12 Jun, 2015 - Comments: 0

Christopher Rolland, an analyst at FBR, made a startling statement in a recent report. “At the pace of consolidation set thus far this year, 32% of all U.S. publicly traded semiconductor companies would be acquired in 2015! While this run-rate is not likely sustainable and should slow as the year progresses, we still expect ~15% consolidation rates for the remainder of this cycle (above low-t... » read more

Can Copper Revolutionize Interconnects Again?
By Katherine Derbyshire - 10 Jun, 2015 - Comments: 2

Electromigration and resistivity present serious obstacles to interconnect scaling, as previously discussed. In a copper damascene process, grain growth is constrained by the narrow trenches into which copper is deposited. As the grain size approaches the mean free path of electrons in copper, electron scattering at sidewalls and grain boundaries increases and resistivity jumps. Meanwhile, incr... » read more

Addressing Thin Film Thickness Metrology Challenges Of 14nm BEOL Layers
By KLA - 21 May, 2015 - Comments: 0

This paper describes a method to effectively monitor the film stack at different metal CMP process steps using a spectroscopic ellipsometer metrology tool. By proper modeling of the Cu dispersion and simulating the underlayer film information underneath the Cu pad, a single measurement recipe was developed which can be used to monitor each process step in the metal CMP process with stable and r... » read more

Flash Dance For Inspection And Metrology
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

Manufacturing Bits: March 17
By Mark LaPedus - 17 Mar, 2015 - Comments: 0

EUV source firm seeks help In 2012, a startup called Zplasma came out of stealth mode and introduced its first technology—a next-generation power source for extreme ultraviolet (EUV) lithography. But after much fanfare and hope, Zplasma has been unable to commercialize its EUV source technology. The company has also been unable to attract a development partner or outside funding. And t... » read more

Searching For Rare Earths Again
By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Rare earths are back in the spotlight again. Rare earths are chemical elements found in the Earth’s crust. They are used in cars, consumer electronics, computers, communications, clean energy and defense systems. The big market for rare earths is magnets. In semiconductor production, rare earths are used in high-k dielectrics, CMP slurries and other applications. Last year, the World Tr... » read more

Still Waiting For III-V Chips
By Mark LaPedus - 19 Feb, 2015 - Comments: 0

For years, chipmakers have been searching for an alternative material to replace traditional silicon in the channel for advanced CMOS devices at 7nm and beyond. There’s a good reason, too: At 7nm, silicon will likely run out of steam in the channel. Until recently, chipmakers were counting on III-V materials for the channels, at least for NFET. Compared to silicon, III-V materials provide ... » read more

Balancing On The Color Density Tightrope
By David Abercrombie - 19 Feb, 2015 - Comments: 0

Balancing on wobbly tightropes is something that chip designers get pretty good at. For instance, there is a fine balance between optimizing performance and minimizing leakage in a design layout. Dealing with the new requirements that multi-patterning (MP) introduces into a design flow creates many new tightropes to walk. I tiptoed out on one of the rarely talked about ones in my last article�... » read more

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