Simulation Study Of Vertically Stacked 2D NSFETs


A new technical paper titled "Simulation of Vertically Stacked 2-D Nanosheet FETs" was published by researchers at Università di Pisa and TU Wien. Abstract "We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet... » read more

Early Detection Of C-RES Degradation On High-Current Power Planes


Probe-card or device contactor damage can be dramatic and catastrophic, with yield dropping drastically very quickly. What is not dramatic is the hypothesized slow probe needle or contactor degradation process that might precede catastrophic failure. Such degradation is difficult to detect in the early stages, when probe cards, die, and packages continue to yield normally. A key goal is to dete... » read more

Balancing Parallel Test Productivity With Yield & Cost


Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

Potential Of 2D Semi-Metallic PtSe2 As Source/Drain Contacts For 2D Material FETs


A technical paper titled “Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts” was published by researchers at Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University. Abstract: "In this ... » read more

GaN Devices: Properties and Performance At Extremely High Temperatures


A new technical paper titled "High temperature stability of regrown and alloyed Ohmic contacts to AlGaN/GaN heterostructure up to 500 °C" was published by researchers at MIT, Technology Innovation Institute, Ohio State University, Rice University and Bangladesh University of Engineering and Technology. Abstract "This Letter reports the stability of regrown and alloyed Ohmic contacts to A... » read more

Using Palladium To Address Contact Issues Of Buried Oxide Thin Film Transistors


A new technical paper titled "Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway" was published by researchers at Tokyo Institute of Technology and National Institute for Materials Science (NIMS). Abstract "Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures... » read more

Estimating the Embedded Gate Resistance to Reproduce SiC MOSFET Circuit Performance (ROHM)


A technical paper titled “Improved Scheme for Estimating the Embedded Gate Resistance to Reproduce SiC MOSFET Circuit Performance” was published by researchers at ROHM Company. Abstract: "The intrinsic gate resistance ( Rg_in) , which is a novel resistance factor embedded in transistors, was determined for silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFE... » read more

Reducing Contact Resistance in Developing Transistors Based On 2D Materials


A new technical paper titled "WS2 Transistors with Sulfur Atoms Being Replaced at the Interface: First-Principles Quantum-Transport Study" was published by researchers at National Yang Ming Chiao Tung University. Abstract "Reducing the contact resistance is one of the major challenges in developing transistors based on two-dimensional materials. In this study, we perform first-principles ... » read more

Modeling and Thermal Analysis of 3DIC


A new technical paper titled "Heat transfer in a multi-layered semiconductor device with spatially-varying thermal contact resistance between layers" was published by researchers at UT Arlington. "This work presents a theoretical model to determine the steady state temperature distribution in a general M-layer structure with spatial variation in thermal contact resistance between adjacent la... » read more

Functional-Engineered MXene Transistors


A new technical paper titled "High-throughput design of functional-engineered MXene transistors with low-resistive contacts" was published by researchers at Indian Institute of Science (IISc) Bangalore. Abstract (partial): "Two-dimensional material-based transistors are being extensively investigated for CMOS (complementary metal oxide semiconductor) technology extension; nevertheless, down... » read more

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