Next-Gen Design Challenges

By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

Dealing With ECOs In Complex Designs

By Ed Sperling - 22 Jan, 2020 - Comments: 0

Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Planning For 5G And The Edge

By Ed Sperling - 23 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss 5G and edge computing with Rahul Goyal, vice president in the technology and manufacturing group at Intel; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; Rob Aitken, R&D fellow at Arm; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows are excerpts of that conversation. Part one i... » read more

Process Corner Explosion

By Ann Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

Process Variation Not A Solved Issue

By Ann Mutschler - 09 Aug, 2018 - Comments: 4

Semiconductor Engineering sat down to talk about process variation in advanced nodes, and how design teams are coping, with Christoph Sohrmann, a member of the Advanced Physical Verification group in Fraunhofer’s Division of Engineering of Adaptive Systems (EAS); Juan Rey, vice president of engineering at Mentor, A Siemens Business; and Stephen Crosher, CEO of Moortec Semiconductor. What foll... » read more

Pain Points At 7nm

By Ed Sperling - 24 Mar, 2016 - Comments: 3

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

Experts At The Table: The Growing Signoff Headache

By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

Stuck In The Corners

By Ann Mutschler - 24 Feb, 2011 - Comments: 0

It’s common for semiconductor design teams to spend 60% to 70% of product development time on verification, which is why verification has bubbled to the top of the management chain as a concern. Executives worry about the predictability of their product development cycle because so much of it is dependent on successful execution of verification, the ability to achieve coverage closure and the... » read more

Experts At The Table: The Trouble With Corners

By Ed Sperling - 09 Sep, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss corners with PV Srinivas, senior director of engineering at Mentor Graphics; Dipesh Patel, vice president of engineering for physical IP at ARM; Lisa Minwell, director of technical marketing at Virage Logic; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation. LPE: As we get to 22nm we’re... » read more

Experts At The Table: The Trouble With Corners

By Ed Sperling - 27 Aug, 2010 - Comments: 0

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Knowledge Centers
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tag: corners

Next-Gen Design Challenges

Dealing With ECOs In Complex Designs

Planning For 5G And The Edge

Process Corner Explosion

Process Variation Not A Solved Issue

Pain Points At 7nm

Experts At The Table: The Growing Signoff Headache

Stuck In The Corners

Experts At The Table: The Trouble With Corners

Experts At The Table: The Trouble With Corners