tag: critical dimensions

Patterning Problems Pile Up
By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

Next Challenge: Contact Resistance
By Mark LaPedus - 23 Jun, 2016 - Comments: 0

In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact. Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or conta... » read more

Inside Inspection And Metrology
By Mark LaPedus - 18 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about inspection, metrology and other issues with Mehdi Vaez-Iravani, vice president of advanced imaging technologies at Applied Materials. What follows are excerpts of that conversation. SE: Today, the industry is working on a new range of complex architectures, such as 3D NAND and finFETs. For these technologies, the industry is clearly struggling... » read more

Multiple Patterns, Multiple Trade-Offs
By David Abercrombie - 11 Dec, 2014 - Comments: 0

As the saying goes, “There is no such thing as a free lunch.” That is a reality that chip designers have had to live by from the beginning. From the advent of the first design rule, it was clear that you couldn’t just do anything you wanted. In the end, everything comes down to trade-offs. Whether it’s area, speed, leakage, noise sensitivity, or drive current, doing something to impr... » read more

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