Next Challenge: Contact Resistance

New materials and tools are needed to solve an issue no one worried about in the past.


In chip scaling, there is no shortage of challenges. Scaling the finFET transistor and the interconnects are the biggest challenges for current and future devices. But now, there is another part of the device that’s becoming an issue—the contact.

Typically, the contact doesn’t get that much attention, but the industry is beginning to worry about the resistance in the contacts, or contact resistance, in leading-edge chip designs.

Basically, a chip has two main structures—the transistor and interconnects. The transistor, which serves as a switch in a device, resides on the bottom of the structure. On top of the transistor, there are several levels. These levels consist of tiny copper wiring schemes, or interconnects, which are connected throughout the chip.

The contact is a tiny and distinct structure, which connects the transistor with the first layer of copper interconnects in a device. A chip can have billions of contacts. For example, Apple’s latest A9 application processor consists of 2 billion transistors and 10 to 15 metal layers. Based on a 16nm/14nm finFET process, the A9 also has an astounding 6 billion tiny contacts to the transistor.

The problem is that the contacts are becoming smaller at each node, which in turn is leading to unwanted contact resistance in devices. Resistance represents the difficulty of a current passing through a conductor.

“If you want a high performance device, it’s becoming very difficult because of the contact,” said Jonathan Bakke, product manager at Applied Materials. “Contact resistance is slowing down the transistor.”

There is another way to look at contact resistance. “You do all of this work to make the transistor fast,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “It’s great, but you can’t get the signals in and out (if there is too much contact resistance).”

Fortunately, the industry is able to scale the contact and its associated metallization scheme, which is based on tungsten. But at some point, there are fears that tungsten will run out of steam, prompting the industry to explore new and future metallization schemes, including those based on cobalt.

The challenges
Basically, the transistor, interconnects and contacts are manufactured in the fab. Using a multitude of process steps, the transistor is manufactured in the front-end-of-the-line (FEOL) in a fab.

The interconnects, which have their own set of process steps, are made in the backend-of-the-line (). There are a multitude of challenges in the BEOL. For example, the interconnects—the tiny copper wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.

Like the interconnects, the contacts also have some issues. Technically, the contacts and local interconnects are fabricated in the middle-of-the-line (MOL) in the fab.

Basically, the contact is a tiny three dimensional structure with a gap. Using a deposition process, the gap within the contact is filled with a conductive material called tungsten. This process is referred to as gap fill. Traditionally, tungsten is used for metal fill applications due to its low resistivity and conformal characteristics.

The gap within the structure is sometimes called a tungsten plug. The tungsten plug is sandwiched between a liner and barrier material. “The barrier is CVD or ALD TiN (titanium nitride),” Applied’s Bakke said. “The liner/nucleation material is a doped ALD W (tungsten).”

At the 16nm/14nm node, the critical dimension (CD) of the contact is approximately 25nm. At the 10nm node, the CDs of the contact are expected to range from 10nm to 15nm.

As the contact becomes smaller, the volume of the tungsten conductor material decreases. “By the time you have a 15nm CD, you have very little tungsten material in the contact feature, only on the order of about 3nm,” Bakke said. “This has a big impact on resistance, because conductor resistance increases very quickly at these CDs.”

At those CDs, unwanted seams may form within the structure, possibly leading to killer defects. There are other contributors to contact resistance in a device, such as high resistive layers and multiple film interfaces.

What is the end result? “The feature sizes of the contact are getting smaller, leading to higher aspect ratios,” Lam’s Hemker said. “If the resistance of that contact is too high, that will end up impacting the device.”

The solutions
Fortunately, there are solutions to the problem, but chipmakers may need to re-engineer the contact at 10nm and beyond. The idea is to increase the volume of tungsten in the contact without creating unwanted seams in the structure.

The obvious solution would be to make the liner and barrier layers thinner, thereby increasing the tungsten conductor volume. That won’t work, however. In the MOL contact, the liner/barrier materials have reached their fundamental thickness limits.

“In the case of the barrier and liner, these actually can’t be scaled any thinner,” Applied’s Bakke said. “They have already been scaled down so much.”

So to solve that problem, Applied Materials has devised a new plasma-enhanced chemical vapor deposition (PECVD) process, which lowers contact resistance by up to 90%. The process enables a metal-organic tungsten film, which is capable of replacing the barrier and nucleation layers. In effect, the film performs the functions of both. “The low resistivity film allows for greater volume of tungsten,” Bakke said.

“The PECVD W film uses a proprietary chemical, where the reactive plasma is used to break down the ligands,” Bakke said in a recent paper. “The final film composition is >80% W, and the atoms from the decomposed ligands are bonded to the W. The amorphous character and the dopants in the film from the ligand lead to good adhesion properties to dielectrics down to ~20 A and F barrier properties at ~30 A.”

So with the technology, there is a path to extend tungsten for the MOL contacts. But for how long?

“It would be ideal to extend tungsten as far as possible,” said David Fried, chief technology officer at Coventor. “It’s a low resistance material and it’s a well-known CVD deposition process.”

According to Fried, however, there are three issues working against tungsten:

• Dimensional scaling makes the holes smaller.
• The complexity of underlying topology makes patterning more difficult.
• More complex process flows have more process variations.

“Many people are starting to think about Co liners as a way to potentially open up the window for subsequent depositions, whether plating of copper in the BEOL, or even CVD tungsten in the MOL,” Fried said.

So, in the future, some are proposing to replace tungsten with cobalt for the contacts in the MOL. “While silicide contact resistance has already emerged as a performance-limiter, by (the) ≤10nm nodes, the W-based MOL resistances in smaller contact structures also becomes significant,” said Vimal Kamineni, member of the technical staff at GlobalFoundries, in a recent presentation. “There is a critical need to find an alternative barrier for W-based metallization, or an alternative barrier/fill metallurgy, to meet resistance requirements.”

As part of a research project in the lab, GlobalFoundries and IBM Research investigated the use of cobalt as a replacement for tungsten in the contacts. According to researchers, CVD-enabled cobalt has three main advantages for the MOL contacts:

• Cobalt doesn’t require the nucleation layers, which, in turn, provides more room for bulk metal.
• The materials do not attack the Ti liner, enabling barrier thickness scaling.
• It can be annealed at reasonable thermal budgets, thereby enabling grain growth and reflow for high aspect ratio features and a void-free seamless fills.

Researchers from GlobalFoundries and IBM developed a cobalt metallization process for the contacts. This process used a TiN barrier and a Ti liner.

The results were promising, as cobalt demonstrated a 2.5x line resistance benefit over tungsten. Cobalt isn’t exactly ready for prime time, however. “Though Co-based MOL metallization is promising, several potential issues must be addressed, including electromigration reliability, gate stack reliability, and any Co ferromagnetic effects on high current and high-frequency electrical signals,” Kamineni said.

Others are working on a slightly different variation of the technology. Lam Research, for one, has devised an electroless deposition technique that selectively grows cobalt materials in vias in the BEOL, followed by conventional copper metallization for the trench.

Cobalt is promising, but for now, the industry will continue to use traditional tungsten. “The GF/IBM paper helps demonstrate that resistance is a major industry concern for the MOL,” Applied’s Bakke said. “But the industry prefers to use a material with the infrastructure in place and with solved integration flows. Any material change is difficult for the contact/MOL, but Applied Materials is working closely with our customers on multiple possibilities, including a Co fill.”

Related Stories
Interconnect Challenges Grow
RC Delay: Bottleneck To Scaling
7nm Fab Challenges

Leave a Reply

(Note: This name will be displayed publicly)