Blog Review: Sept. 25

By Jesse Allen - 25 Sep, 2019 - Comments: 0

Mentor's Dave Rich points out that unexpected values from a constraint solver can often be explained by how Verilog expression evaluation rules affect the solution space of SystemVerilog constraints. Cadence's Madhavi Rao points to the need for new and updated safety and cybersecurity standards for autonomous vehicles and highlights one of the most challenging parts of AV deployment. A Sy... » read more

The New CXL Standard

By Ed Sperling - 16 Sep, 2019 - Comments: 0

Gary Ruggles, senior staff product marketing manager at Synopsys, digs into the new Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs. » read more

Week In Review: Design, Low Power

By Jesse Allen - 15 Mar, 2019 - Comments: 0

M&A Nvidia will acquire Mellanox for $6.9 billion in cash, the largest deal in the chipmaker's history. Traditionally a PC GPU company, Nvidia has made a push into high-performance computing, particularly for AI workloads. Founded in 1999, Israel-based Mellanox focuses on end-to-end Ethernet and InfiniBand interconnect solutions and services for servers and storage. According to Nvidia, Me... » read more

Introduction to the Compute Express Link Standard

By Synopsys - 24 Jul, 2016 - Comments: 0

By Gary Ruggles, Sr. Product Marketing Manager, Synopsys Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a Host and Device is required. A consortium to enable this new standard was recently announced simultaneously with the release of the CXL 1.0 specification. Th... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: CXL

Blog Review: Sept. 25

The New CXL Standard

Week In Review: Design, Low Power

Introduction to the Compute Express Link Standard