FOPLP Gains Traction in Advanced Semiconductor Packaging

By Gregory Haley - 21 Nov, 2024 - Comments: 0

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

Advanced Packaging Drives Test And Metrology Innovations

By Gregory Haley - 12 Nov, 2024 - Comments: 0

Advanced packaging has become a focal point for innovation as the semiconductor industry continues to push for increased transistor density and better performance. But the pace of change is accelerating, making it harder for the entire ecosystem to keep up with those changes. In the past, major developments were roughly on an 18-month to 2-year cadence. Today, this is happening every few mon... » read more

3D Metrology Meets Its Match In 3D Chips And Packages

By Laura Peters - 11 Jun, 2024 - Comments: 0

The pace of innovation in 3D device structures and packages is accelerating rapidly, driving the need for precise measurement and control of feature height to ensure these devices are reliable and perform as expected throughout their lifetimes. Expansion along the z axis is already well underway. One need look no further than the staircase-like 3D NAND stacks that rise like skyscrapers to p... » read more

Inspection, Metrology Issues In Advanced Packages

By Gregory Haley - 08 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about how to inspect and measure smaller features across large areas in advanced packaging, with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; John Hoffman, computer vision engineering manager at Nordson Test & Measurement; and Jiangtao Hu, senior technology director at O... » read more

Closing The Test And Metrology Gap In 3D-IC Packages

By Gregory Haley - 12 Dec, 2023 - Comments: 0

The industry is investing in more precise and productive inspection and testing to enable advanced packages and eventually, 3D ICs. The next generations of aerospace, automotive, smartphone, and wearable tech most likely will be powered by multiple layers of intricately connected silicon, a stark departure from the planar landscapes of traditional integrated circuits. These 3D-ICs, compos... » read more

Striking A Balance In Acoustic Inspection

By Ed Sperling - 12 Jun, 2023 - Comments: 0

Sound energy is a quick way to to spot voids, delamination, cracks, and other possible defects that are accessible from outside the chip or package, as well as some defects that are inside of chips. But acoustic inspection also is highly sensitive to different materials with different polarities, which can change the reflection of sound waves. Bill Zuckerman, product marketing manager at Nordso... » read more

From Lab To Fab: Increasing Pressure To Fuse IC Processes

By Gregory Haley - 06 Jun, 2023 - Comments: 0

Test, metrology, and inspection are essential for both the lab and the fab, but fusing them together so that data created in one is easily transferred to the other is a massive challenge. The chip industry has been striving to bridge these separate worlds for years, but the economics, speed, and complexity of change require a new approach. The never-ending push toward smaller, better-defined... » read more

Five Smart Ways To Improve EV Battery Production

By Muge Deniz Meiller - 06 Jun, 2023 - Comments: 0

Batteries and battery management systems are the heart of today's electric vehicles. These components define the performance, safety, and driving range of more than 16.5 million1 electric vehicles currently on the road. As electric vehicle and battery manufacturers continue to look for ways to increase the efficiency and speed of their production processes, many turn to Nordson EFD for prec... » read more

3D Structures Challenge Wire Bond Inspection

By Karen Heyman - 09 May, 2023 - Comments: 1

Adding more layers in packages is making it difficult, and sometimes impossible, to inspect wire bonds that are deep within the different layers. Wire bonds may seem like old technology, but it remains the bonding approach of choice for a broad swath of applications. This is particularly evident in automotive, industrial, and many consumer applications, where the majority of chips are not de... » read more

Case Study – Rohinni Micro LEDs

By CyberOptics - 11 Apr, 2023 - Comments: 0

Rohinni combines vision, execution and micron-scale electronics to make impossible products possible. Using its patented device-placement technologies, Rohinni, together with its joint venture partners, enables bringing innovative products to market in high volumes, and at greatly reduced cost. Click here to read more. » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?