DDR5 Client Chipset


This episode of Ask the Experts discusses DDR5 for client systems with John Eble, VP of Product Marketing, Memory Interface Chips at Rambus. Topics discussed include: The need for advanced chipsets for DDR5 client DIMMs The role of the DDR5 Client Clock Driver (CKD) and its use cases The AI applications driving the need for greater memory performance in client systems Find more... » read more

Chip Industry Week in Review


The Biden-Harris Administration announced preliminary terms with HP for $50 million in direct funding under the CHIPs and Science Act to support the expansion and modernization of HP’s existing microfluidics and microelectromechanical systems (“MEMS”) facility in Corvallis, Oregon. CHIPS for America launched the CHIPS Metrology Community, a collaborative initiative designed to advance ... » read more

Chip Industry Week in Review


Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Memory System Benchmarking, Simulation, And Application Profiling Via A Memory Stress Framework


A technical paper titled “A Mess of Memory System Benchmarking, Simulation and Application Profiling” was published by researchers at Barcelona Supercomputing Center, Unversitat Politecnica de Catalunya, and Micron Technology (Italy). Abstract: "The Memory stress (Mess) framework provides a unified view of the memory system benchmarking, simulation and application profiling. The Mess benc... » read more

Rowhammer Exploitation On AMD Platforms, DDR4 DDR5 (ETH Zurich)


A new technical paper titled "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" was published by researchers at ETH Zurich. The work will be presented at USENIX Security Symposium in August 2024. Abstract: "AMD has gained a significant market share in recent years with the introduction of the Zen microarchitecture. While there are many recent Rowhammer attacks launched from Intel CPU... » read more

How To Stop Row Hammer Attacks


Row hammer is a well-publicized target for cyberattacks on DRAM, and there have been attempts to stop these attacks in DDR4 and DDR5, but with mixed results. The problem is that as density increases, distance decreases, making it more likely that flipped bit cell in one row can disturb a bit cell in another, and that bits flipped across an entire row can flip another row. Steven Woo, fellow and... » read more

Package Propagation Delay Dependency Of Advanced Fly-By Routing For Next Generation DDR5


Package signal transit delay is an important parameter for high-speed designs like DDR5. Package delay along with PCB delay dictates the data rates of DDR5 interface running at 4.0 Gbps and beyond. From DDR3 (third generation DDR) onwards, daisy chain routing has been widely used as it can support high data rate operations by providing smaller trace stubs and capacitive loadings. Even so, beyon... » read more

A Novel Approach To Mitigating RowHammer Attacks And Improving Server Memory System Reliability


A technical paper titled “RAMPART: RowHammer Mitigation and Repair for Server Memory Systems” was published by researchers at Rambus. Abstract: "RowHammer attacks are a growing security and reliability concern for DRAMs and computer systems as they can induce many bit errors that overwhelm error detection and correction capabilities. System-level solutions are needed as process technology... » read more

Closing The Performance Gap Between DRAM And AI Processors


As the workhorse of semiconductor memory, DRAM holds a unique place in the industry thanks to its large storage capacity and ability to feed data and program code to the host processor quickly. Lately, this unsung hero of the circuit board has been taking a backseat to its logic counterparts, as a wave of high-performance FPGAs, CPUs, GPUs, TPUs and custom accelerator ASICs emerges to meet t... » read more

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)


A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. Abstract: "We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the perfo... » read more

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