tag: debug

Tail End Latency And Server Debug
By UltraSoC - 11 Apr, 2018 - Comments: 0

The rise of the heterogeneous multicore processor has enabled a massive increase in the ability of data centers to deliver advanced services to billions of users worldwide. But the complexity that is now possible has made the optimization of these services difficult to achieve. Providers of heterogeneous multicore SoCs have an opportunity to deliver the tools to make optimization of highly dist... » read more

When AI Goes Awry
By Ed Sperling - 26 Mar, 2018 - Comments: 0

The race is on to develop intelligent systems that can drive cars, diagnose and treat complex medical conditions, and even train other machines. The problem is that no one is quite sure how to diagnose latent or less-obvious flaws in these systems—or better yet, to prevent them from occurring in the first place. While machines can do some things very well, it's still up to humans to devise... » read more

Debugging Debug
By Brian Bailey - 22 Feb, 2018 - Comments: 2

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Tech Talk: 7nm Process Variation
By Ed Sperling - 17 Jan, 2018 - Comments: 0

Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

Which Verification Engine?
By Ed Sperling - 02 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Is Verification Falling Behind?
By Brian Bailey - 21 Dec, 2017 - Comments: 1

Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

Enabling Synchronized Hardware Software Debug With Verdi
By Synopsys - 13 Dec, 2017 - Comments: 0

Verdi HW SW Debug is an instruction-accurate embedded processor debug solution that offers fully synchronized views between hardware, as RTL or gate-level design models, and software, as C or assembly code enabling co-debug between RTL and software. To read more, click here. » read more

Big Challenges, Changes For Debug
By Ann Mutschler - 04 Dec, 2017 - Comments: 1

By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

Electromagnetic (EM) Crosstalk Analysis: Unlocking the Mystery
By Magdy Abadir - 09 Nov, 2017 - Comments: 0

Ignoring electromagnetic crosstalk is highly risky and can cause significant time-to-market delays as well significant cost over runs. Most current SoC design flows fundamentally ignore inductance and EM effects, and the term “EM crosstalk analysis” may sound Greek to them. This short article provides a quick overview of the basic steps involved in doing EM crosstalk analysis as part of an ... » read more

A Simple Way To Debug IIP-Based Designs And SoCs
By Synopsys - 27 Sep, 2017 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the concept of debugging with “real time simulation data” using Verdi Transaction Debug Platform (protocol analyzer, waveform viewer, source code browser) and show its benefits by taking a few generic USB... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy