Chip Industry Week In Review


The chip industry is well on its way to hit $1 trillion in revenue by the end of its decade. Several analyst firms released 2024 annual results and 2025 predictions: Worldwide semiconductor revenue reached $626 billion in 2024, an 18% increase versus 2023, according to preliminary Gartner report. Memory revenue grew about 70%  2024 versus 2023. The firm forecasts that HBM will make up 19%... » read more

Chip Industry Technical Paper Roundup: Jan. 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=398 /] Find all technical papers here. » read more

Loss Processes in Electrochemically Charged Semiconductor Nanocrystal Films (TU Delft)


A new technical paper titled "Where Do the Electrons Go? Studying Loss Processes in the Electrochemical Charging of Semiconductor Nanomaterials" was published by researchers at Delft University of Technology. Abstract "Electrochemical charging of films of semiconductor nanocrystals (NCs) allows precise control over their Fermi level and opens up new possibilities for use of semiconductor NC... » read more

Chip Industry Technical Paper Roundup: Nov. 11


New technical papers recently added to Semiconductor Engineering’s library: [table id=381 /] More Reading Technical Paper Library » read more

Effectiveness of Hardware Fuzzing In Detecting Memory Vulnerabilities


A new technical paper titled "Fuzzerfly Effect: Hardware Fuzzing for Memory Safety" was published by researchers at Technical University of Darmstadt, Texas A&M University and Delft University of Technology. Abstract: "Hardware-level memory vulnerabilities severely threaten computing systems. However, hardware patching is inefficient or difficult post-fabrication. We investigate the eff... » read more

Chip Industry Technical Paper Roundup: June 10


New technical papers added to Semiconductor Engineering’s library this week. [table id=232 /] More ReadingTechnical Paper Library home » read more

Physics-Based Digital Twin of a Thermally Aged Flip-Chip Package (TU Delft, NXP)


A technical paper titled “Modelling thermomechanical degradation of moulded electronic packages using physics-based digital twin” was published by researchers at Delft University of Technology and NXP Semiconductors. Abstract: "Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume with... » read more

Chip Industry Technical Paper Roundup: May 7


New technical papers added to Semiconductor Engineering’s library this week. [table id=223 /] More ReadingTechnical Paper Library home » read more

Voltage Reference Architectures For Harsh Environments: Quantum Computing And Space


A technical paper titled “Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K” was published by researchers at Delft University of Technology, QuTech, Kavli Institute of Nanoscience Delft, and École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in ... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. The Japanese government approved $3.9 billion in funding for chipmaker Rapidus to expand its foundry business, of which 10% will be invested in advanced packaging. This is in addition to the previously announced $2.18 billion in funding. In a meeting next week, the U.S. and Japan are expected to cooperate on increasing semiconductor development a... » read more

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