Chip Industry Technical Paper Roundup: Nov. 11


New technical papers recently added to Semiconductor Engineering’s library: [table id=381 /] More Reading Technical Paper Library » read more

Effectiveness of Hardware Fuzzing In Detecting Memory Vulnerabilities


A new technical paper titled "Fuzzerfly Effect: Hardware Fuzzing for Memory Safety" was published by researchers at Technical University of Darmstadt, Texas A&M University and Delft University of Technology. Abstract: "Hardware-level memory vulnerabilities severely threaten computing systems. However, hardware patching is inefficient or difficult post-fabrication. We investigate the eff... » read more

Chip Industry Technical Paper Roundup: June 10


New technical papers added to Semiconductor Engineering’s library this week. [table id=232 /] More ReadingTechnical Paper Library home » read more

Physics-Based Digital Twin of a Thermally Aged Flip-Chip Package (TU Delft, NXP)


A technical paper titled “Modelling thermomechanical degradation of moulded electronic packages using physics-based digital twin” was published by researchers at Delft University of Technology and NXP Semiconductors. Abstract: "Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume with... » read more

Chip Industry Technical Paper Roundup: May 7


New technical papers added to Semiconductor Engineering’s library this week. [table id=223 /] More ReadingTechnical Paper Library home » read more

Voltage Reference Architectures For Harsh Environments: Quantum Computing And Space


A technical paper titled “Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K” was published by researchers at Delft University of Technology, QuTech, Kavli Institute of Nanoscience Delft, and École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "This article presents a family of sub-1-V, fully-CMOS voltage references adopting MOS devices in ... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. The Japanese government approved $3.9 billion in funding for chipmaker Rapidus to expand its foundry business, of which 10% will be invested in advanced packaging. This is in addition to the previously announced $2.18 billion in funding. In a meeting next week, the U.S. and Japan are expected to cooperate on increasing semiconductor development a... » read more

Chip Industry Technical Paper Roundup: Jan 2


New technical papers added to Semiconductor Engineering’s library this week. [table id=180 /] More ReadingTechnical Paper Library home » read more

Analog Planar Memristor Device: Developing, Designing, and Manufacturing


A new technical paper titled "Analog monolayer SWCNTs-based memristive 2D structure for energy-efficient deep learning in spiking neural networks" was published by researchers at Delft University of Technology and Khalifa University. Abstract: "Advances in materials science and memory devices work in tandem for the evolution of Artificial Intelligence systems. Energy-efficient computation... » read more

More Efficient Side-Channel Analysis By Applying Two Deep Feature Loss Functions


A technical paper titled “Beyond the Last Layer: Deep Feature Loss Functions in Side-channel Analysis” was published by researchers at Nanyang Technological University, Radboud University, and Delft University of Technology. Abstract: "This paper provides a novel perspective on improving the efficiency of side-channel analysis by applying two deep feature loss functions: Soft Nearest Neig... » read more

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