Optimize Physical Verification Cost Of Ownership

By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Fast-Track Your Early SoC Design Exploration And Verification

By Nermeen Hossam - 26 Sep, 2019 - Comments: 0

By Nermeen Hossam and John Ferguson Most advanced node system-on-chip (SoC) designs are very large, and very complex. They typically contain many blocks and intellectual property (IP) that perform specialized functions, such as computation, internal communications, and signal processing. These blocks are often built by separate teams or IP suppliers, and integrated into the SoC layout. Howev... » read more

Moving Beyond Geometries: Context-Aware Verification Improves Design Quality And Reliability

By Sherif Hany - 25 Apr, 2019 - Comments: 0

Context-aware checks integrate physical and electrical information to evaluate a wide range of design conditions, from advanced design rule compliance, to circuit and reliability verification, to design optimization and finishing. Automated context-aware checking provides designers with actionable results that improve both debugging efficiency and verification precision. Introduction Many p... » read more

How Qualcomm Got Faster Signoff DRC Convergence

By Srinivas Velivala - 28 Mar, 2019 - Comments: 0

Qualcomm Incorporated designs and markets wireless telecommunications products and services that are the foundational technologies that others build upon, from mobile processors to embedded platforms, Bluetooth products, and cellular modems. In the fast-moving mobile phone market in which Qualcomm competes, companies who can get to market more quickly gain a strong competitive advantage, along ... » read more

Design For Advanced Packaging

By Brian Bailey - 08 Nov, 2018 - Comments: 0

Advanced packaging techniques are viewed as either a replacement for Moore's Law scaling, or a way of augmenting it. But there is a big gap between the extensive work done to prove these devices can be manufactured with sufficient yield and the amount of attention being paid to the demands advanced packaging has on the design and verification flows. Not all advanced packaging places the same... » read more

Get Ready For Integrated Silicon Photonics

By Brian Bailey - 12 Apr, 2018 - Comments: 1

Long-haul communications and data centers are huge buyers of photonics components, and that is leading to rapid advances in the technology and opening new markets and opportunities. The industry has to adapt to meet the demands being placed on it and solve the bottlenecks in the design, development and fabrication of integrated silicon photonics. "Look at the networking bandwidth used across... » read more

EUV’s New Problem Areas

By Mark LaPedus - 19 Mar, 2018 - Comments: 2

Extreme ultraviolet (EUV) lithography is moving closer to production, but problematic variations—also known as stochastic effects—are resurfacing and creating more challenges for the long-overdue technology. GlobalFoundries, Intel, Samsung and TSMC hope to insert [gettech id="31045" comment="EUV"] lithography into production at 7nm and/or 5nm. But as before, EUV consists of several compo... » read more

Integrated Photonics (Part 3)

By Brian Bailey - 12 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the status of integrated photonics with Twan Korthorst, CEO for PhoeniX Software; Gilles Lamant, distinguished engineer for [getentity id="22032" e_name="Cadence"]; Bill De Vries, director of marketing for Lumerical Solutions; and Brett Attaway, director of EPDA solutions at AIM Photonics, SUNY Polytechnic Institute. What follows are excerpts of tha... » read more

Optimization Challenges For 10nm And 7nm

By Brian Bailey - 11 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032"... » read more

Raising The IQ Of Your MEMS-Based IC Design Flow

By Nicolas Williams - 15 Oct, 2015 - Comments: 0

By Nicolas Williams and Qi Jing Internet of Things (IoT) applications depend on smart objects that interact with the real world. So your IoT project is likely to contain ICs that integrate micro electro-mechanical systems (MEMS), such as accelerometers, pressure sensors, motors, and microphones that acquire data for analysis. These projects are finding their way into automobiles, phones, and... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: design-rule checking