Use Advanced DFT And Silicon Bring Up To Accelerate AI Chip Design

By Siemens EDA - 07 Dec, 2023 - Comments: 0

The market for AI chips is growing quickly, with the 2022 revenue of $20B expected to grow to over $300B by 2030. To keep up with the demand and stay competitive, AI chip designers set aggressive time-to-market goals. Design teams looking for ways to shave significant time off chip development time can look to advanced DFT and silicon bring up techniques described in this paper, including hiera... » read more

An Entangled Heterarchy

By Brian Bailey - 09 Nov, 2023 - Comments: 1

For decades, a form of structural hierarchy has been the principal means of handling complexity in chip design. It's not always perfect, and there is no ideal way in which to divide and conquer because that would need to focus on the analysis being performed. In fact, most systems can be viewed from a variety of different hierarchies, equally correct, and together forming a heterarchy. The e... » read more

DRAM Test And Inspection Just Gets Tougher

By Anne Meixner - 07 Nov, 2023 - Comments: 0

DRAM manufacturers continue to demand cost-effective solutions for screening and process improvement amid growing concerns over defects and process variability, but meeting that demand is becoming much more difficult with the rollout of faster interfaces and multi-chip packages. DRAM plays a key role in a wide variety of electronic devices, from phones and PCs to ECUs in cars and servers ins... » read more

Rebalancing Test And Yield In IC Manufacturing

By Gregory Haley - 07 Nov, 2023 - Comments: 0

Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Connection Perfection

By Ramsay Allen - 07 Nov, 2023 - Comments: 0

Whether you are a DFT engineer or a SoC designer, connectivity validation will no doubt be a top priority when taking steps to guarantee the functionality and reliability of your device. SoC designs continue to grow in both size and complexity to meet the ever-growing performance and power demands associated with modern technology. To keep up with this fast-paced evolution, the corresponding D... » read more

Designing Automotive ICs For Cybersecurity

By Mohammed Abdelwahid - 02 Nov, 2023 - Comments: 0

The day has already arrived when we need to be concerned about the cybersecurity of our cars. An average modern car includes about 1400 ICs and many of them are used in sophisticated applications, like autonomous driving and vehicle-to-everything (V2X) communication. The security of road vehicles is an important issue to automakers and OEMs but is rooted in the IC devices that power the vehicle... » read more

eFPGA Architectural Improvements That Lower Test Cost And Increase Quality

By Geoff Tate - 02 Nov, 2023 - Comments: 0

More than 40 chips have been licensed to use EFLX eFPGA and >20 chips are working in silicon. Big customers like Renesas are planning high volume families of chips using embedded FPGA. As a result, we have gained extensive experience and knowledge in almost 10 years of doing eFPGA especially in production test for cost reduction and reliability improvement. eFPGA DFT and MBIST for high q... » read more

EDA’s Role Grows For Preventing And Identifying Failures

By Karen Heyman - 08 Jun, 2023 - Comments: 0

The front end of design is becoming more tightly integrated with the back end of manufacturing, driven by the rising cost and impact of failures in advanced chips and critical applications. Ironically, the starting point for this shift is failure analysis (FA), which typically happens when a device fails to yield, or worse, when it is returned due to some problem. In production, that leads t... » read more

Chiplet Planning Kicks Into High Gear

By Ann Mutschler - 25 May, 2023 - Comments: 0

Chiplets are beginning to impact chip design, even though they are not yet mainstream and no commercial marketplace exists for this kind of hardened IP. There are ongoing discussions about silicon lifecycle management, the best way to characterize and connect these devices, and how to deal with such issues as uneven aging and thermal mismatch. In addition, a big effort is underway to improve... » read more

From Known Good Die To Known Good System With UCIe IP

By Manuel Mota - 11 May, 2023 - Comments: 0

Multi-die systems are made up of several specialized functional dies (or chiplets) that are assembled in the same package to create the complete system. Multi-die systems have recently emerged as a solution to overcome the slowing down of Moore’s law by providing a path to scaling functionality in the packaged chip in a way that is manufacturable with good yield. Additionally, multi-die sy... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?