tag: DFT

Yield Is Top Issue For MicroLEDs
By Laura Peters - 11 Oct, 2022 - Comments: 0

MicroLED display makers are marching toward commercialization, with products such as Samsung’s The Wall TV and Apple’s smart watch expected to be in volume production next year or in 2024. These tiny illuminators are the hot new technology in the display world, enabling higher pixel density, better contrast, lower power consumption, and higher luminance in direct sunlight — while consu... » read more

Test Data Streaming For The Next Generation Of Designs
By Rahul Singhal - 08 Sep, 2022 - Comments: 0

Semiconductor chips have been evolving to meet the demands of rapidly transforming applications, and so has the test technology to meet the test goals of those chips. Going back two decades or so, the applications were limited and the designs were simpler, thus the concerns about power, performance and area (PPA), turn-around time, re-use and time-to-market, etc., were important but not as crit... » read more

Enabling Test Strategies For 2.5D, 3D Stacked ICs
By Laura Peters - 08 Sep, 2022 - Comments: 0

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield.  Many changes need to fall into place to make side-by-side 2.5D and 3D stacking approaches cost-effective, particularly for companies looking to integrate chiplets from different vendors. Today, nearly all of t... » read more

Testing The Stack: DFT Is Ready For 3D Devices
By Martin Keim - 08 Sep, 2022 - Comments: 0

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

Affordable And Comprehensive Testing Of 3D Stacked Die Devices
By Siemens EDA - 07 Sep, 2022 - Comments: 0

Developers of high-end semiconductor products who face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time. How then, can designers manage DFT for these new 3D devices? In this paper, we outli... » read more

Semiconductor Test: Staying Ahead Of Nanodevices
By Tucker Davis - 07 Jun, 2022 - Comments: 0

In the semiconductor fabrication process, engineers continue to innovate, enabling smaller transistors and higher density circuits. The transition to finFETs allowed 7nm and 5nm processes to realize circuits of amazing density, and the progress of nanosheet transistors provides confidence in the future advancement of digital circuit cost reduction and performance improvement. As individual t... » read more

Automation Of Shared Bus Memory Test With Tessent MemoryBIST
By Siemens EDA - 12 Apr, 2022 - Comments: 0

New requirements in automotive, artificial intelligence (AI), and processor applications have resulted in increased use of memory-heavy IP. Memory-heavy IPs for these applications are optimized for high performance, and they will often have a single access point for testing the memories. Tessent MemoryBIST provides an out-of-the-box solution for using this single access point, or shared bus int... » read more

Automate Memory Test Through A Shared Bus Interface
By Harshitha Kodali - 12 Apr, 2022 - Comments: 0

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

Software-Driven and System-Level Tests Drive Chip Quality
By Bryon Moyer - 08 Mar, 2022 - Comments: 0

Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

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