tag: die-to-die

Pinpointing Timing Delays Can Improve Chip Reliability
By Anne Meixner - 09 May, 2023 - Comments: 0

Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

Die-To-Die Chiplet Communication
By Paul McLellan - 11 Mar, 2021 - Comments: 0

At CadenceLIVE Americas 2020, one of the most viewed videos was by Samsung Foundry's Kevin Yee and Cadence's Tom Wong, titled "Let’s Talk About Chips (Chiplets), Baby…It’s All About D2D!" They went for this title because it reminded them of the lyrics of an '80s song...which they proceeded to sing. Process and packaging trends Tom led off with a look at the trends in semiconducto... » read more

Different Levels Of Interconnects
By Ed Sperling - 17 Jun, 2020 - Comments: 0

The interconnect hierarchy from metal 0 in a semiconductor all the way up to racks of servers. Kurt Shuler, vice president of marketing at Arteris IP, explains why each one is different, and how every level can contribute to latency and performance. » read more

Die-to-Die Connectivity With High-Speed SerDes PHY IP
By Manuel Mota - 12 Mar, 2020 - Comments: 0

Hyperscale data center, artificial intelligence (AI), and networking SoCs have become more complex with advanced functionalities and have reached maximum reticle sizes. Designers are partitioning such SoCs in smaller modules requiring ultra- and extra-short reach links for inter-die connectivity with high data rates. The die-to-die connectivity must also ensure reliable links with extremely low... » read more

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