tag: double patterning

Double Patterning: Challenges And Possible Solutions In Parasitics Extraction
By David Abercrombie - 16 Aug, 2012 - Comments: 0

By Dusan Petranovic and David Abercrombie Double patterning (DP), as the simplest form of multi-patterning techniques, is receiving lots of attention right now. The need for double patterning techniques is driven by the physical limits of the dimensions that can be resolved with current light sources and lenses, as well as by the difficulties and delays in deploying next-generation lithography... » read more

Revisiting Moore’s Law
By Ed Sperling - 09 Aug, 2012 - Comments: 0

Moore’s Law was predicted to end at 1 micron. It was predicted to die off twice by Gordon Moore himself. And it has vacillated between 18 and 24 months on at least a couple of occasions since it was first introduced in 1965. From a technology perspective, there is no reason to assume it will ever die. It has gone from microns to nanometers and it can continue well into the picometer range.... » read more

Experts At The Table: Challenges At 20nm
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

Litho Community Meets And Votes
By Marc David Levenson - 31 Jul, 2012 - Comments: 0

Every 18 months or so, the leading lithography lights of the IEEE meet in an off-the-record workshop to discuss the state and future of our craft. This year’s event took place amid the restored colonial splendor of Williamsburg Virginia in June. Co-chairs Mordechai Rothschild and Lars Liebmann assembled a technical program that covered not only lithography for semiconductor manufacturing, but... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung El... » read more

Looking Into The Future
By Ed Sperling - 31 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design sat down with Juan Rey, senior director of engineering for Calibre at Mentor Graphics, about multipatterning, design rules and silicon photonics. [youtube vid=KoH5TwmFWDM] » read more

Experts At The Table: Pain Points
By Ed Sperling - 27 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: What comes next requires a lot of guesswork in the design, do... » read more

Experts At The Table: Pain Points
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

The Ins And Outs Of Directed Self-Assembly
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus H.S. Phillip Wong, professor of electrical engineering at Stanford University and one of the leading experts on directed self-assembly (DSA) technology, sat down to discuss the future of this approach with Semiconductor Manufacturing & Design. With funding from the Semiconductor Research Corp. (SRC), Stanford is exploring contact-hole patterning and the design infrastructur... » read more

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