Experts At The Table: Multipatterning

First of three parts: Different challenges at 20nm and 14nm; just how ready are we at 20nm; is patterning the future or the wrong direction?


By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics. What follows are excerpts of that conversation.

SMD: We’ve been hearing for a long time about EUV, but at this point it may not even be commercially viable at 14nm. So what do we do about that?
Liebmann: We have to keep the roadmap going, but we have to focus on performance scaling and cost per function scaling—and perhaps more so than pitch scaling. This whole idea that we’ll do double patterning and triple patterning and quadruple patterning, at some point the cost-per-function equation starts to degrade. I predict we’ll get away from these very rigorous node definitions and introduce new elements such as FinFETs to get a power/performance boost rather than focusing on 70% pitch scaling every two years because Moore’s Law says so. We have more options.

SMD: So how do we get out of this?
Aitken: That’s an excellent question, but I’m not sure there’s an equally excellent answer. The first challenge is that we have to be clear what we’re talking about. With 28nm, 22nm and 20nm, in some ways we’ve already lost touch with what those numbers actually mean. It’s similar to a size-12 shoe. It’s not 20% bigger than a size-10 shoe. It’s just somewhat bigger. In the same way, 22nm is somewhat smaller than 28nm but we’ve already lost some of the 70% pitch scaling Lars mentioned. So then we’re left with, ‘What’s actually scaling and what are the limiters?’ We’re trying to push those limiters. We need to apply more double patterning to more layers, and eventually that stops making cost-effective sense. It’s not obvious EUV will be ready even in time for 14nm, and at 10nm we’re into a lot of complexity even with EUV. There is a general issue with patterning, too. There are so many complexities associated with double patterning and so many flavors—stitching or not stitching, self-aligned or not self-aligned.
Capodieci: On double patterning, we will use it in technology development and production. It is complex and costly, but it is the only technology we have available. What’s really interesting is going beyond double patterning to triple patterning and quadruple patterning. Everybody has said at some point it will have to stop. The discussion beyond double patterning is that it makes us realize the insanity, for lack of a better word, of trying to do patterning at all. The reality is we have to stop doing patterning. That’s the wrong way to go beyond 14nm. We need to assemble and build. Patterning from the top down and creating an entire design methodology basically creates very complex systems. Then we try to create a physical design by superimposing our will onto hard matter. The hard matter pushes back. Photons don’t scale. Atoms don’t scale. And thermally, the voltage doesn’t scale. We need to discuss triple patterning, but only with the notion of destroying it.
Lin: It’s something we have to cope with at 20nm and 14nm.
White: From a tools perspective, double patterning will be necessary at 20nm. We absolutely see it, given all partners we have worked with, at 14nm. But at 14nm it will expand beyond double patterning. Whether it’s triple patterning is still a question for our customers. From an EDA perspective we perceive part of our normal business going forward. It’s an adjunct of on top of physical verification.
Capodieci: There are good solutions in place for double patterning. But in terms of design solutions as a whole, we are not there. Just because we have a signoff tool does not mean the entire ecosystem is ready. There are point solutions.
Geronimi: What is surprising is that double patterning is working quite well. This is coming from processes at other nodes where we have used design co-optimization, but this is the first time for design enablement.

SMD: Where are we with double patterning and directed self-assembly?
Liebmann: As Jean-Pierre said, we have solved the problem of double patterning for 20nm. There are no alternatives. We have rules, tools and methodologies. I would declare this problem solved.
Lin: I agree. We’re still smoothing out the kinks, but there are no major showstoppers.
Liebmann: So from here on, we can focus on the future, which involves directed self-assembly.
Aitken: There is an existence of tools at 20nm and there are various companies that have done it. But I think we’re a long way from saying these solutions have all of the kinks worked out.
Liebmann: And I would agree with that. As each new company creates a new test chip, we are having to work with them on this process, doing verification and taping out.
Aitken: One classic one we’ve been looking at recently is that when you have double-patterned metal layers you no longer have the concept of a best-case, worst-case that you had previously. You have fairly correlated situations where pattern one and pattern two get close to each other, creating a best case in one situation and a worst case in the other that migrates across the die. You have to have a method of dealing with that for timing closure. It’s not obvious how to do that with a lot of the tools today.
Capodieci: This is what I have been saying, as well. We have the solution, yes. It works, yes. But the deployment of this solution to a larger community without additional work isn’t possible, and it’s not a trivial amount of work. As engineers, we don’t just want a solution. What we want is a high-volume design to be in production. That isn’t an insurmountable problem, but it hasn’t been demonstrated yet.

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