tag: DRAM

Machine Learning’s Growing Divide
By Brian Bailey - 11 Jan, 2018 - Comments: 7

[getkc id="305" kc_name="Machine learning"] is one of the hottest areas of development, but most of the attention so far has focused on the cloud, algorithms and GPUs. For the semiconductor industry, the real opportunity is in optimizing and packaging solutions into usable forms, such as within the automotive industry or for battery-operated consumer or [getkc id="76" kc_name="IoT"] products. ... » read more

A New Memory Contender?
By Mark LaPedus - 02 Jan, 2018 - Comments: 1

Momentum is building for a new class of ferroelectric memories that could alter the next-generation memory landscape. Generally, ferroelectrics are associated with a memory type called ferroelectric RAMs (FRAMs). Rolled out by several vendors in the late 1990s, FRAMs are low-power, nonvolatile devices, but they are also limited to niche applications and unable to scale beyond 130nm. While... » read more

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract: "The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh ... » read more

Foundry Challenges in 2018
By Mark LaPedus - 27 Dec, 2017 - Comments: 6

The silicon foundry business is expected to see steady growth in 2018, but that growth will come with several challenges. On the leading edge, GlobalFoundries, Intel, Samsung and TSMC are migrating from the 16nm/14nm to the 10nm/7nm logic nodes. Intel already has encountered some difficulties, as the chip giant recently pushed out the volume ramp of its new 10nm process from the second half ... » read more

Will Fab Tool Boom Cycle Last?
By Mark LaPedus - 18 Dec, 2017 - Comments: 2

Fab equipment spending is on pace for a record year in 2017, and it now appears that momentum could continue into 2018. Fab tool vendors found themselves in the midst of an unexpected boom cycle in 2017, thanks to enormous demand for equipment in [getkc id="208" comment="3D NAND"] and, to a lesser degree, [getkc id="93" kc_name="DRAM"]. In the logic/foundry business, however, equipment deman... » read more

The Next 5 Years Of Chip Technology
By Ed Sperling - 18 Dec, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

Pushing DRAM’s Limits
By Kevin Fogarty - 14 Dec, 2017 - Comments: 1

If humans ever do create a genuinely self-aware artificial intelligence, it may well exhibit the frustration of waiting for data arrive. The access bandwidth of DRAM-based computer memory has improved by a factor of 20x over the past two decades. Capacity increased 128x during the same period. But latency improved only 1.3x, according to Kevin Chang, a researcher at Carnegie Mellon Universit... » read more

Shortages Hit Packaging Biz
By Mark LaPedus - 11 Dec, 2017 - Comments: 1

Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up earlier this year, but the problem has been growing and spreading since then. Supply imbalances reached a boiling point in the third and fourth quarters of this yea... » read more

New Drivers For I/O
By Brian Bailey - 13 Nov, 2017 - Comments: 0

Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

Making high-capacity data caches more efficient
By Technical Paper Link - 24 Oct, 2017 - Comments: 4

Source: Researchers from MIT, Intel, and ETH Zurich Xiangyao Yu (MIT), Christopher J. Hughes (Intel), Nadathur Satish (Intel) Onur Mutlu (ETH Zurich), Srinivas Devadas (MIT) Technical Paper link MIT News article As the transistor counts in processors have gone up, the relatively slow connection between the processor and main memory has become the chief impediment to improving comp... » read more

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