tag: DRAM

What Happened To DSA?
By Mark LaPedus - 19 May, 2016 - Comments: 2

Directed self-assembly (DSA) was until recently a rising star in the next-generation lithography (NGL) landscape, but the technology has recently lost some of its luster, if not its momentum. So what happened? Nearly five years ago, an obscure patterning technology called [gettech id="31046" t_name="DSA"] burst onto the scene and began to generate momentum in the industry. At about that t... » read more

2.5D Becomes A Reality
By Ed Sperling - 11 May, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Rethinking Main Memory
By Hunglin Hsu - 10 May, 2016 - Comments: 3

With newer, bigger programs and more apps multitasking simultaneously, the answer to making any system run faster, from handheld to super computer, was always just to add more DRAM. . . and more, and more and more. From data centers to wearables, that model no longer works. By offloading the storage of programs to less expensive solid-state drives (SSDs) and only using a small amount of exp... » read more

Why This Roadmap Matters
By Ed Sperling - 05 May, 2016 - Comments: 0

The semiconductor industry is now officially looking beyond PCs and servers, establishing metrics and guidance for existing and developing market segments rather than just focusing on how to get to the next process nodes. The IEEE's International Roadmap for Devices and Systems marks a fundamental shift in the industry. The uncertainty that has ensued ever since the introduction of 3D transi... » read more

High-Bandwidth Memory
By eSilicon - 27 Apr, 2016 - Comments: 0

High-bandwidth memory (HBM) is a JEDEC-defined standard, dynamic random access memory (DRAM) technology that uses through-silicon vias (TSVs) to interconnect stacked DRAM die. In its first implementation, it is being integrated with a system-on-chip (SoC) logic die using 2.5D silicon interposer technology. This white paper explains HBM’s value proposition, and how these five companies make... » read more

Rightsizing Challenges Grow
By Ed Sperling - 20 Apr, 2016 - Comments: 0

Rightsizing chip architectures is getting much more complicated. There are more options to choose from, more potential bottlenecks, and many more choices about what process to use at what process node and for which markets and price points. Rightsizing is a way of targeting chips to specific application needs, supplying sufficient performance while minimizing power and cost. It has been a to... » read more

Power/Performance Bits: April 19
By Jesse Allen - 19 Apr, 2016 - Comments: 0

Ferroelectric non-volatile memory Scientists from the Moscow Institute of Physics and Technology (MIPT), the University of Nebraska, and the University of Lausanne in Switzerland succeeded in growing ultra-thin (2.5-nanometer) ferroelectric films based on hafnium oxide that could potentially be used to develop non-volatile memory elements called ferroelectric tunnel junctions. The film was g... » read more

It’s All About DRAM
By Ed Sperling - 14 Apr, 2016 - Comments: 4

For decades, the starting point for compute architectures was the processor. In the future, it likely will be the DRAM architecture. Dynamic random access memory always has played a big role in computing. Since IBM's Robert Dennard invented DRAM back in 1966, it has become the gold standard for off-chip memory. It's fast, cheap, reliable, and at least until about 20nm, it has scaled quite n... » read more

Using Multi-Channel Connections for Optimized LPDDR4 Power & Performance
By Marc Greenberg - 14 Apr, 2016 - Comments: 0

LPDDR4, the latest double data rate synchronous DRAM for mobile applications, includes a number of features that enable SoC design teams to reduce power consumption of discrete DRAM in mobile devices. Desktop devices like PCs and servers commonly utilize DDR devices mounted on dual inline memory modules (DIMM) hosted on 64-bit wide buses. This board-level solution allows field-upgradeable DRAM ... » read more

Many Paths To Hafnium Oxide
By Katherine Derbyshire - 31 Mar, 2016 - Comments: 0

Equipment and materials suppliers often talk about the fragmentation of integrated circuit processing. While the number of manufacturers has gone down, the diversity of the underlying semiconductor market has increased. Low-power processors for mobile devices, non-volatile memory for solid state disks, and dedicated graphics processors all have different requirements from the traditional ind... » read more

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